DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 505

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
DEMO9S12XEP100
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Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
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Chapter 13
Analog-to-Digital Converter (ADC12B16CV1)
13.1
The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital
converter. Refer to device electrical specifications for ATD accuracy.
13.1.1
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V01.00
V01.01
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
8-, 10-, or 12-bit resolution.
Conversion in Stop Mode using internally generated clock
Automatic return to low power after conversion sequence
Automatic compare with interrupt for higher than or less/equal than programmable value
Programmable sample time.
Left/right justified result data.
External trigger control.
Sequence complete interrupt.
Analog input multiplexer for 16 analog input channels.
Special conversions for V
1-to-16 conversion sequence lengths.
Continuous conversion mode.
Multiple channel scans.
Configurable external trigger functionality on any AD channel or any of four additional trigger
inputs. The four additional trigger inputs can be chip external or internal. Refer to device
specification for availability and connectivity.
Configurable location for channel wrap around (when converting multiple channels in a sequence).
Introduction
Revision Date
Features
04 Mar. 2008
13 Oct. 2005
Sections
Affected
MC9S12XE-Family Reference Manual , Rev. 1.23
RH
, V
Table 13-1. Revision History
RL
- Initial version
corrected reference to DJM bit
, (V
RL
+V
RH
)/2.
Description of Changes
505

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