DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 909

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.3.2.5
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU or XGATE.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
Freescale Semiconductor
ECCRIX[2:0]
Offset Module Base + 0x0004
Reset
IGNSF
Field
Field
CCIE
2-0
7
4
W
R
CCIE
ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is
being read. See
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
Flash Configuration Register (FCNFG)
0
7
generated
25.3.2.8).
= Unimplemented or Reserved
0
0
6
Section 25.3.2.13, “Flash ECC Error Results Register
Figure 25-9. Flash Configuration Register (FCNFG)
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 25-14. FECCRIX Field Descriptions
Table 25-15. FCNFG Field Descriptions
0
0
5
IGNSF
0
4
Description
Description
Chapter 25 256 KByte Flash Module (S12XFTM256K2V1)
0
0
3
(FECCR),” for more details.
0
0
2
FDFD
0
1
Section
25.3.2.7)
FSFD
0
0
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