DEMO9S08DZ60 Freescale Semiconductor, DEMO9S08DZ60 Datasheet - Page 351

• Manufacturer Part Number: DEMO9S08DZ60
• Description: BOARD DEMO
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08DZ60

• Contents: Board, Cable, CD
• Processor To Be Evaluated: MC9S08DZ60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08D
• Kit Contents: MC9S08DZ60 Board, Software, Cables, Connectors
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08DZ60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 17-2
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge
to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD
pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal
during this period.
Freescale Semiconductor
SYNCHRONIZATION
PERCEIVED START
(TARGET MCU)
BDC CLOCK
UNCERTAINTY
TRANSMIT 1
TRANSMIT 0
OF BIT TIME
HOST
HOST
shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.
Figure 17-2. BDC Host-to-Target Serial Bit Timing
MC9S08DZ60 Series Data Sheet, Rev. 4
TARGET SENSES BIT LEVEL
10 CYCLES
EARLIEST START
Chapter 17 Development Support
OF NEXT BIT
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