P0304 Terasic Technologies Inc, P0304 Datasheet - Page 48

• Manufacturer Part Number: P0304
• Description: DE2-70 CALL FOR ACADEMIC PRICING
• Manufacturer: Terasic Technologies Inc
• Type: FPGAr

Specifications of P0304

• Contents: DE2-70 Board, Power Supply, Cables, Plastic cover and software
• For Use With/related Products: Cyclone II 2C70
• For Use With: P0033 - BOARD ADAPTER HSMC TO GPIOP0006 - BOARD ADAPTER THDB-SUMP0001 - MODULE DIGITAL CAMERA 5MP (D5M)P0307 - KIT DEV 4.3" LCD TOUCH PANEL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DE2-70

DE2-70 User Manual
5.7 Using VGA
The DE2-70 board includes a 16-pin D-SUB connector for VGA output. The VGA synchronization
signals are provided directly from the Cyclone II FPGA, and the Analog Devices ADV7123 triple
10-bit high-speed video DAC is used to produce the analog data signals (red, green, and blue). The
associated schematic is given in Figure 5.12 and can support resolutions of up to 1600 x 1200 pixels,
at 100 MHz.
Figure 5.12. VGA circuit schematic.
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on
various educational web sites (for example, search for “VGA signal timing”). Figure 5.13 illustrates
the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An
active-low pulse of specific duration (time a in the figure) is applied to the horizontal
synchronization (hsync) input of the monitor, which signifies the end of one row of data and the
start of the next. The data (RGB) inputs on the monitor must be off (driven to 0 V) for a time period
called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c).
During the data display interval the RGB data drives each pixel in turn across the row being
displayed. Finally, there is a time period called the front porch (d) where the RGB signals must
again be off before the next hsync pulse can occur. The timing of the vertical synchronization (vsync)
is the same as shown in Figure 5.13, except that a vsync pulse signifies the end of one frame and the
start of the next, and the data refers to the set of rows in the frame (horizontal timing). Table 5.9 and
5.10 show, for different resolutions, the durations of time periods a, b, c, and d for both horizontal
and vertical timing.
Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be
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