P0304 Terasic Technologies Inc, P0304 Datasheet - Page 82

• Manufacturer Part Number: P0304
• Description: DE2-70 CALL FOR ACADEMIC PRICING
• Manufacturer: Terasic Technologies Inc
• Type: FPGAr

Specifications of P0304

• Contents: DE2-70 Board, Power Supply, Cables, Plastic cover and software
• For Use With/related Products: Cyclone II 2C70
• For Use With: P0033 - BOARD ADAPTER HSMC TO GPIOP0006 - BOARD ADAPTER THDB-SUMP0001 - MODULE DIGITAL CAMERA 5MP (D5M)P0307 - KIT DEV 4.3" LCD TOUCH PANEL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DE2-70

address in the packet is identical to the MAC address of the DE2-70 board. If the packet received
does have the same MAC address or is a broadcast packet, the DM9000A will accept the packet and
send an interrupt to the Nios II processor. The processor will then display the packet contents in the
Nios II IDE console window.
Demonstration Setup, File Locations, and Instructions
Figure 6.12 illustrates the setup for this demonstration.
 Project directory: DE2_70_NET
 Bit stream used: DE2_70_NET.sof
 Nios II Workspace: DE2_70_NET\Software
 Plug a CAT5 loop-back cable into the Ethernet connector of DE2-70
 Load the bit stream into the FPGA
 Run the Nios II IDE under the workspace DE2_70_NET
 Click on the Compile and Run button
 You should now be able to observe the contents of the packets received (64-byte packets
sent, 68-byte packets received because of the extra checksum bytes)
Figure 6.11. Packet sending and receiving using the Nios II processor.
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DE2-70 User Manual