R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 14
![KIT DEV FOR SH7203](/photos/9/24/92406/r0k572030s000be_sml.jpg)
R0K572030S000BE
Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K572030S000BE
Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
SuperH
I
• From 16x1 to 800x600 pixels
• 11/2/4/6/8/16/18/24 bpp (bit per
• 1/2/4 bpp grayscale
• 8-bit frame rate controller
• Supports data formats for
• Supports variations of the burst
• Supports inversion of the output
• Hardware-rotation mode is
• Power control function
• A unified memory architecture
I
• MAC (Media Access Control) functions
(SVGA) can be supported
pixel) with 24-bit color pallet
STN/dual-STN/TFT panels
(8/12/16/18/24-bit bus width)
length in reading from the
synchronous DRAM to achieve
high data-read speeds
signal, if necessary, to match the
LCD panel’s signal polarity
included to support the use of
landscape-format LCD panels as
portrait-format LCD panels
is adopted for the LCD controller
so the image data for display is
stored in system memory
– Data frame assembly/disassembly
– CSMA/CD link management
– CRC/PAD processing
– Built-in FIFO (2KB for Tx, up to 8KB for Rx)
– Supports full-duplex and half-duplex
– Short packets/long packets
LCD Controller
Ethernet MAC
(IEEE802.3-compliant frame)
(collision avoidance, processing in case of collision)
transmission/reception
®
Family of Microcontrollers & Microprocessors
LCD Controller Block Diagram
EtherC Function Block Diagram
P Clock
LCLK
CKIO
MAC
ECMR.DM
Command/Status
Transmit Control
Receive Control
Interface
PSR.LMON
PIR
• Compatible with MII (Media Independent Interface),
• Magic Packet
• CAM (Contents Addressable Memory) Interface
Register
RMII (Reduced MII), and GMII (Gigabit MII)
standards
– Converts 8-bit data stream from MAC layer
– Station management (STA) functions
– 18 TTL-level signals (5V or 3.3V interface)
– Variable transfer rate: 10/100/1000Mbps
to MII nibble data stream (4 bits)
(based on PHY chip features)
TX
RX
Li Bus Interface
Generator
Li Bus
Interface
Clock
™
MII
(with wake-on-LAN output)
clk
LCDC
MDC/
MCIO
LINK
Power Control
MII
512 bytes
Pallet
RAM
Line Buffer
2.4 kbytes
PHYSTS
PHY Chip
CL1
CL2
FLM
LCD 15 0
DON
VCPWC
VEPWC
M/DISP
DS
12