R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 9

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

I
• Supports single-precision (32 bits)
• 10-stage floating instruction
• Supports IEEE754-compliant
• Floating-point registers:
• (Single-precision x 16 words,
• 32-bit CPU-FPU floating-point
• Supports FMAC
• Supports FDIV (divide)
• Supports FLDI0/FLDI1
• 3D graphics instructions
• 4-dimensional vector
• 4-dimensional vector (FIPR)
• Instruction execution times
and double-precision (64 bits)
pipeline (SH-4A)
data types and exceptions
32 bits x 16 words x 2 banks
or double-precision x 8 words)
x 2 banks
communication register (FPUL)
(multiply-and-accumulate)
instruction
and FSQRT (square root)
instructions
(load constant 0/1) instructions
(single-precision only)
conversion and matrix
operations (FTRV): 4 cycles
(pitch), 8 cycles (latency)
inner product: 1 cycle (pitch),
5 cycles (latency)
– Latency
– Pitch
SuperH On-Chip Floating
Point Co-processor
Architectural Features
(FMAC/FADD/FSUB/FMUL):
3 cycles (single-precision),
8 cycles (double-precision)
(FMAC/FADD/FSUB/FMUL):
1 cycle (single-precision),
6 cycles (double-precision)
Hybrid RISC/DSP Architecture • Floating Point Features
Versatility of the floating point co-processor
Powerful 4-way FPU for 3-D graphics
16-tap, 40-sample block FIR (1.6 MACs/cycle)
1024-point, radix-2 FFT (35.4 cycles)
In1
In2
MULTIPLICATION
INNER PRODUCT
Surface judgement
brightness
Multiplication
Multiplication
3-D graphics
3-D graphics
geometry
geometry
128-bit Floating Point Vector Engine: DSP/SIMD Instructions
y
y
y
y
i
i+1
i+2
i+3
calculation
=
-1
A single DIF butterfly
x
x
x
x
source
i
i+1
i+2
i+3
STAGE 1
x
x
x
x
i+1
i
i+1
i+2
W=a+jb
A single SuperH instruction, FIPR, can perform this
x
x
x
x
i-2
i-1
i
i+1
Y1
Y2
Y3
1
x
x
x
x
i-3
i-2
i-1
i-
inner-product multiplication every cycle.
=
Out1
Out2
x
c11
c21
c31
c41
c0
c1
c2
c3
c12
c22
c32
c42
+ ... +
c13
c23
c33
c43
b
1
0
a
ray
I
-b
c14
c24
c34
c44
0
1
a
=
-b
-a
1
0
d
x
x
x
x
x
r1 r2
i-12
i-11
i-10
i-9
-a
0
1
b
x
x
x
x
x1
x2
x3
1
i-13
i-12
i-11
i-10
x
STAGE 4
x
x
x
x
r3 0
i-14
i-13
i-12
i-11
In1_r
In1_i
In2_r
In2_i
instruction, FTRV,
A single SuperH
can perform this
every 4 cycles.
matrix-vector
multiplication
x
x
x
x
i-15
i-14
i-13
i-12
=
x
x
Out1_r
Out1_i
Out2_r
Out2_i
d1
d2
d3
0
c12
c13
c14
c15
Rn