R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 39

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

I
External bus width mode input
External bus input/output
Appendix A-2: Architecture of SH-2A Series
High-performance
JTAG input/output
user debugging
Pin function
Bus state
controller
controller
controller
interface
(H-UDI)
Cache
(BSC)
(PFC)
Port
Port
CPU core
SH-2A
General input/output
cache memory
Instruction
8 Kbytes
I/O ports
Power-down
Port
control
mode
CKIO input/output,
generator (CPG)
Clock mode input
cache memory
XTAL output,
Clock pulse
EXTAL input,
Operand
8 Kbytes
D/A converter
Analog output
Port
(DAC)
Port
IRQOUT output
On-chip RAM
bus controller
MRES input,
128 Kbytes
RES input,
PINT input,
Peripheral
controller
NMI input,
IRQ input,
Interrupt
(INTC)
Port
A/D converter
ADTRG input
Analog input,
(ADC)
Port
Multi-function
timer pulse
Timer pulse
input/output
(MTU2)
unit 2
Port
input/output
interface 3
I
I
2
(IIC3)
2
C bus
Port
C bus
Architecture Diagrams
access controller
Direct memory
Multi-function
timer pulse
User break
Timer pulse
input/output
controller
(MTU2S)
(DMAC)
(UBC)
subset
unit 2
Port
Serial input/output
communication
with FIFO
interface
Serial
(SCIF)
CPU memory access bus (M bus)
Port
CPU instruction fetch bus (F bus)
Port output
enable 2
POE input
(POE2)
Internal bus (I bus) (B clock)
Port
Peripheral bus (P clock)
WDTOVF output
match timer
Watchdog
Compare
(WDT)
timer
(CMT)
Port
UBCTRG output
DREQ input
DACK output
TEND output
CPU bus
(C bus)
(I clock)