C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 143
C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Bits7:
Bit6:
Bits5–0: USBADDR: USB0 Indirect Register Address
BUSY
R/W
Bit7
BUSY: USB0 Register Read Busy Flag
This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to
initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The
target address and BUSY bit may be written in the same write to USB0ADR. After BUSY is
set to ‘1’, hardware will clear BUSY when the targeted register data is ready in the
USB0DAT register. Software should check BUSY for ‘0’ before writing to USB0DAT.
Write:
0: No effect.
1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits.
Read:
0: USB0DAT register data is valid.
1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid.
AUTORD: USB0 Register Auto-read Flag
This bit is used for block FIFO reads.
0: BUSY must be written manually for each USB0 indirect register read.
1: The next indirect register read will automatically be initiated when software reads
USB0DAT (USBADDR bits will not be changed).
These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 15.2
lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT
will target the register indicated by the USBADDR bits.
AUTORD
R/W
Bit6
SFR Definition 15.2. USB0ADR: USB0 Indirect Address
R/W
Bit5
R/W
Bit4
Rev. 1.4
R/W
Bit3
USBADDR
R/W
Bit2
R/W
Bit1
C8051F320/1
R/W
Bit0
SFR Address:
00000000
Reset Value
0x96
143
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