C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 155

• Manufacturer Part Number: C8051F320-TB
• Description: BOARD PROTOTYPING W/C8051F320
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320-TB

• Contents: Board
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F320
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bit3:
Bit2:
Bit1:
Bit0:
Bit7
R
-
USB Register Definition 15.13. CMINT: USB0 Common Interrupt
SOF: Start of Frame Interrupt
Set by hardware when a SOF token is received. This interrupt event is synthesized by hard-
ware: an interrupt will be generated when hardware expects to receive a SOF event, even if
the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
RSTINT: Reset Interrupt-pending Flag
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
RSUINT: Resume Interrupt-pending Flag
Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend
mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
SUSINT: Suspend Interrupt-pending Flag
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hard-
ware when Suspend signaling is detected on the bus. This bit is cleared when software
reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.
Bit6
R
-
Bit5
R
-
Bit4
R
-
Rev. 1.4
SOF
Bit3
R
RSTINT
Bit2
R
RSUINT
Bit1
R
C8051F320/1
SUSINT
Bit0
R
USB Address:
00000000
Reset Value
0x06
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