C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 83
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C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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- Download datasheet (2Mb)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
9.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
TMR2RLL
TMR3CN
TMR3H
TMR3L
TMR3RLH
TMR3RLL
USB0ADR
USB0DAT
USB0XCN
VDM0CN
XBR0
XBR1
0x84–0x86, 0xAB-0xAF,
0xB4, 0xB5, 0xBF, 0xC7,
0xCE, 0xCF, 0xD2, 0xD3,
0xDF, 0xE3, 0xE5, 0xF5
Bits7–0: DPL: Data Pointer Low.
Register
R/W
Bit7
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
R/W
Bit6
Address
0xCA
0xD7
0xFF
0xE1
0xE2
0x91
0x95
0x94
0x93
0x92
0x96
0x97
Table 9.3. Special Function Registers (Continued)
SFR Definition 9.1.
R/W
Bit5
Timer/Counter 2 Reload Low
Timer/Counter 3Control
Timer/Counter 3 High
Timer/Counter 3Low
Timer/Counter 3 Reload High
Timer/Counter 3 Reload Low
USB0 Indirect Address Register
USB0 Data Register
USB0 Transceiver Control
VDD Monitor Control
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Reserved
R/W
Bit4
DPL: Data Pointer Low Byte
Rev. 1.4
R/W
Bit3
Description
R/W
Bit2
R/W
Bit1
C8051F320/1
R/W
Bit0
SFR Address:
00000000
Reset Value
0x82
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