C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 44
C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F320/1
5.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track-
ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initi-
ate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins
on the rising edge of CNVSTR (see Figure 5.4). Tracking can also be disabled (shutdown) when the device
is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX set-
tings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling
Time Requirements” on page 45.
44
(AD0CM[2:0] = 000, 001,010
Timer 1, Timer 3 Overflow
Write '1' to AD0BUSY,
(AD0CM[2:0] = 100)
Timer 0, Timer 2,
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing
AD0TM = 1
AD0TM = 0
SAR Clocks
AD0TM = 1
AD0TM = 0
011, 101)
CNVSTR
Clocks
Clocks
SAR
SAR
Low Power
or Convert
Low Power
or Convert
Track or
A. ADC0 Timing for External Trigger Source
Convert
Track or Convert
B. ADC0 Timing for Internal Trigger Source
1
1
Track
Track
2
2
3
3
4
4
Rev. 1.4
1
5
5
2
6
6
Convert
3
7
7
4
8
8
5
9 10 11 12
9
Convert
6
10 11
Convert
Convert
7
8
12 13 14
9
13 14
10 11
15 16 17
12 13 14
Low Power Mode
Track
Low Power
Mode
Track
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