C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 230

• Manufacturer Part Number: C8051F320-TB
• Description: BOARD PROTOTYPING W/C8051F320
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320-TB

• Contents: Board
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F320
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F320/1
20.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then the state of the Port
pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge caused
the capture.
230
Timer Overflow
PCA Counter/
W
P
M
1
6
n
PCA Module 0
PCA Module 1
PCA Module 2
PCA Module 3
PCA Module 4
(for n = 0 to 4)
PCA0CPMn
E
C
O
M
n
C
A
P
P
n
(CCF0)
(CCF1)
(CCF2)
(CCF3)
(CCF4)
C
A
P
N
n
M
A
T
n
O
G
T
n
W
P
M
n
E
C
C
F
n
C
F
C
R
PCA0CN
C
C
F
4
Figure 20.3. PCA Interrupt Block Diagram
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
C
D
L
I
W
D
T
E
PCA0MD
W
D
C
K
L
C
P
S
2
C
P
S
1
0
1
0
1
0
1
0
1
0
1
C
P
S
0
C
E
F
0
1
Rev. 1.4
EPCA0
0
1
EA
0
1
Interrupt
Priority
Decoder