MC56F8323EVME Freescale Semiconductor, MC56F8323EVME Datasheet - Page 130

• Manufacturer Part Number: MC56F8323EVME
• Description: BOARD EVALUATION MC56F8323
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8323EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8322 and MC56F8323
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F8322, MC56F8323
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C, the internal [dynamic component], is classic C*V
56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading
on the external pins of the chip. This is also commonly described as C*V
of the IO cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero
Y-intercept.
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change.
in the IO cells as a function of capacitive load. In these cases:
where:
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found
to be fairly low when averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the
device. Sum the total of all V
0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs
driving 10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,
as it is assumed to be negligible.
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Summation is performed over all output pins with capacitive loads
TotalPower is expressed in mW
Cload is expressed in pF
8mA CMOS 3-State Output Pad with Input-Enabled Pull-Up
4mA CMOS 3-State Output Pad with Input-Enabled Pull-Up
TotalPower = Σ((Intercept + Slope*Cload)*frequency/10MHz)
Table 10-25 IO Loading Coefficients at 10MHz
2
/R or IV to arrive at the resistive load contribution to power. Assume V =
56F8323 Technical Data, Rev. 17
Table 10-25
provides coefficients for calculating power dissipated
2
*F CMOS power dissipation corresponding to the
Intercept
1.15mW
1.3
2
*F, although simulations on two
0.11mW / pF
0.11mW / pF
Slope
Freescale Semiconductor
Preliminary