MC56F8323EVME Freescale Semiconductor, MC56F8323EVME Datasheet - Page 88

BOARD EVALUATION MC56F8323

MC56F8323EVME

Manufacturer Part Number
MC56F8323EVME
Description
BOARD EVALUATION MC56F8323
Manufacturer
Freescale Semiconductor
Type
DSPr
Datasheets

Specifications of MC56F8323EVME

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC56F8322 and MC56F8323
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F83xx
Rohs Compliant
Yes
For Use With/related Products
MC56F8322, MC56F8323
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
6.5.2.3
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will
set the bit, while writing a 1 to the bit will clear it.
6.5.2.4
If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On
Reset or by software. Writing a 0 to this bit position will set the bit while writing a 1 to the bit position will
clear it. Basically, when the EXTR bit is 1, the previous system reset was caused by the external RESET
pin being asserted low.
6.5.2.5
When 1, the POR bit indicates a Power-On Reset occurred some time in the past. This bit can be cleared
only by software or by another type of reset. Writing a 0 to this bit will set the bit, while writing a 1 to the
bit position will clear the bit. In summary, if the bit is 1, the previous system reset was due to a Power-On
Reset.
6.5.2.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.3
Only SIM SCR0 is shown in this section. SIM SCR1, SIM SCR2, and SIM SCR3 are identical in
functionality.
6.5.3.1
This register is reset only by the Power-On Reset (POR). It has no part-specific functionality and is
intended for use by a software developer to contain data that will be unaffected by the other reset sources
(RESET pin, software reset, and COP reset).
6.5.4
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F4.
88
Base + $2
RESET
Read
Write
SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2,
and SIM_SCR3)
Most Significant Half of JTAG ID (SIM_MSH_ID)
COP Reset (COPR)—Bit 4
External Reset (EXTR)—Bit 3
Power-On Reset (POR)—Bit 2
Reserved—Bits 1–0
Software Control Data 1 (FIELD)—Bits 15–0
15
0
Figure 6-5 SIM Software Control Register 0 (SIM_SCR0)
14
0
13
0
12
0
56F8323 Technical Data, Rev. 17
11
0
10
0
9
0
FIELD
8
0
7
0
6
0
5
0
4
0
3
0
Freescale Semiconductor
2
0
1
0
Preliminary
0
0

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