ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 103
![no-image](/images/manufacturer_photos/0/7/729/zilog_sml.jpg)
ZLP128ICE01ZEM
Manufacturer Part Number
ZLP128ICE01ZEM
Description
EMULATOR CRIMZON Z8 ZLP12840
Manufacturer
Zilog
Datasheets
1.ZLP128ICE01ZEM.pdf
(5 pages)
2.ZLP128ICE01ZEM.pdf
(157 pages)
3.ZLP128ICE01ZEM.pdf
(70 pages)
Specifications of ZLP128ICE01ZEM
Interface Type
RS-232, Ethernet, USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3829
- Current page: 103 of 157
- Download datasheet (3Mb)
PS024410-0108
Power-On Reset Timer
Reset/Stop Mode Recovery Status
Voltage Brownout/Standby
Voltage Detection
When power is initially applied to the device, a timer circuit clocked by a dedicated on-
board RC-oscillator provides the Power-On Reset timer function.
The POR timer circuit is a one-shot timer that keeps the internal reset signal asserted long
enough for V
The reset timer is triggered by one of three conditions:
•
•
•
SMR[5] can be cleared to 0 to bypass the POR timer upon a Stop Mode Recovery. This
should only be done when using an external clock that does not require a start-up delay.
Read-only bit SMR[7]=0 if the previous reset was initiated by a power-on reset (including
brown-out or WDT resets). SMR[7]=1 if the previous reset was initiated by a Stop Mode
Recovery.
A power-on, brown-out, or WDT reset restores all registers to their Power-On Reset
defaults. A Stop Mode Recovery restores most registers to their Power-On Reset defaults.
Register bits not reset by a Stop Mode Recovery are highlighted in grey in the register
tables. Register bit SMR[7] is set to 1 instead of reset by a Stop Mode Recovery.
An on-chip Voltage Comparator checks that the V
operation of the device. Reset is globally driven when V
in V
the V
level is returned to above V
normally.
The Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh)
offers an option of monitoring the V
0 of LVD register is set. After Voltage Detection is enabled, the V
Initial power-on or recovery from a Voltage Brownout/standby condition.
Stop Mode Recovery (if register bit SMR[5] = 1)
Watchdog Timer time-out.
DD
DD
causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If
is allowed to stay above V
DD
and the oscillator circuit to stabilize before instruction execution begins.
P R E L I M I N A R Y
BO
, the device performs a power-on reset and functions
RAM
CC
voltage. The Voltage Detection is enabled when bit
, the RAM content is preserved. When the power
DD
is at the required level for correct
DD
falls below V
Resets and Power Management
Product Specification
CC
ZLP12840 OTP MCU
level is monitored in
BO
. A small drop
97
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