ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 106

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

PS024410-0108
Stop Mode Recovery Event Sources
SMR Register Events
Any Port 2 or 3 input pin can be configured to generate a SMR event, either individually
or in a variety of logical combinations. The PartName provides the following registers for
SMR source configuration and status:
•
•
•
•
•
A SMR event occurs if any of the sources defined in the SMR, SMR1, SMR2, and SMR3
registers is active.
The SMR register function is similar to the standard SMR feature used in previous Z8
CPU-compatible parts. Register bits SMR[4:2] are set to select one of six event modes, as
displayed in
the state of SMR[6]; when they are the same, a SMR event is generated.
If SMR[4:2]=000, no event source is selected by SMR. The state SMR[4:2]=001 is
reserved and selects no event in this device.
The logic configured by the SMR register ignores any port pins that are configured as an
output, or that are selected as source pins in registers SMR1 or SMR3. The SMR register
is summarized in
SMR Register—Selects one Port 3, pin 1–3 pin state or one of three Port 2 pin logical
combinations to generate an event when a defined 0 or 1 level occurs.
SMR1 Register—Configure one or more Port 2 input pins (0–7)to latch the latest read
or write value and generate an event when the pin state changes.
SMR2 Register—Selects one of seven Port 2 and 3 pin logical combinations to gener-
ate an event when a defined 0 or 1 level occurs.
SMR3 Register—Configure one or more Port 3 input pins (0–3) to latch the latest read
or write value and generate an event when the pin state changes.
SMR4 Register—Enables routing of SMR events to IRQ1. Indicates whether port data
has been latched for SMR1 or SMR3 event monitoring, and whether the latch was on
a port read or write.
Figure 35
Table 48
on page 101. The output of the corresponding logic is compared to
P R E L I M I N A R Y
on page 102.
Resets and Power Management
Product Specification
ZLP12840 OTP MCU
100