ZLP128ICE01ZEM Zilog, ZLP128ICE01ZEM Datasheet - Page 33

• Manufacturer Part Number: ZLP128ICE01ZEM
• Description: EMULATOR CRIMZON Z8 ZLP12840
• Manufacturer: Zilog

Specifications of ZLP128ICE01ZEM

• Interface Type: RS-232, Ethernet, USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3829

Memory and Registers
PS024410-0108
OTP Program/Constant Memory
The Z8 LXM CPU used in the ZLP12840 family of devices incorporates special features
to extend the available memory space while maintaining the benefits of a Z8
consumer and battery-operated applications.
The ZLP12840 family of devices can address up to 128 KB of one-time programmable
(OTP) memory, used for object code (program instructions and immediate data) and
constant data (ROM tables and data constants). The amount of OTP implemented depends
on the specific device. The OTP memory space is organized in 64 KB pages with the
following characteristics.
Page 0 can contain up to 64 KB of program instructions and constant data. The first 12
bytes of Page 0 are reserved for the six available 16-bit interrupt request (IRQ) vectors.
Upon reset, program execution begins at address 000Ch in Page 0. Execution rolls over to
the bottom of Page 0 if the program counter exceeds the highest Page 0 address (FFFFh).
Page 1, if implemented, can contain up to 64 KB of data constants and tables only. Page 1
cannot contain program instructions or immediate data. Constant data in either page can
be accessed only by the Load Constant (LDC and LDCI) instructions. LDC and LDCI use
16-bit addresses to access OTP memory.
For example, if a ZLP12840 family device contains 96 KB of OTP memory, only the first
64 KB (Page 0) can contain object code; the remaining 32 KB (in Page 1) is available for
constant data. For a ZLP12840 family device with 64 KB or less of total OTP memory, all
OTP memory is available for object code or constant data.
The page accessed by LDC or LDCI depends on the value of Program Memory Page
Register bit 0 (PMPR[0]). Page 0 is accessed if PMPR[0]=0; Page 1 is accessed if
PMPR[0]=1. PMPR[7] enables the page toggle feature. For example, if PMPR[0]=0,
PMPR[7]=1, and a Load Constant and Increment (LDCI) instruction address increments
past FFFFh, the state of PMPR[0] is toggled from 0 to 1, and the next LDCI instruction
addresses 0000h on Page 1.
map for a 128 KB device.
P R E L I M I N A R Y
Figure 8
on page 28 displays the Program/Constant memory
Product Specification
ZLP12840 OTP MCU
Memory and Registers
®
CPU core in
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