PIC18F1320-I/SO Microchip Technology, PIC18F1320-I/SO Datasheet - Page 133

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: IC MCU FLASH 4KX16 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.0
The Enhanced Addressable Universal Synchronous
Asynchronous Receiver Transmitter (EUSART) mod-
ule can be configured as a full-duplex asynchronous
system that can communicate with peripheral devices,
such as CRT terminals and personal computers. It can
also be configured as a half-duplex synchronous
system that can communicate with peripheral devices,
such as A/D or D/A integrated circuits, serial
EEPROMs, etc.
The
implements additional features, including automatic
baud rate detection and calibration, automatic wake-up
on Sync Break reception and 12-bit Break character
transmit. These features make it ideally suited for use
in Local Interconnect Network (LIN) bus systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full duplex) with:
• Synchronous – Master (half duplex) with
• Synchronous – Slave (half duplex) with selectable
The RB1/AN5/TX/CK/INT1 and RB4/AN6/RX/DT/KBI0
pins must be configured as follows for use with the
Universal
Transmitter:
• SPEN (RCSTA<7>) bit must be set ( = 1),
• PCFG6:PCFG5 (ADCON1<5:6>) must be set ( = 1),
• TRISB<4> bit must be set ( = 1) and
• TRISB<1> bit must be set ( = 1).
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These are detailed in on the following pages in
Register 16-1,
respectively.
 2004 Microchip Technology Inc.
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
selectable clock polarity
clock polarity
Note:
Enhanced
ENHANCED ADDRESSABLE
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
Synchronous
Register 16-2
Addressable
Asynchronous
and
USART
Register 16-3,
Receiver
module
16.1
The EUSART may operate in Asynchronous mode
while the peripheral clocks are being provided by the
internal oscillator block. This makes it possible to
remove the crystal or resonator that is commonly
connected as the primary clock on the OSC1 and
OSC2 pins.
The factory calibrates the internal oscillator block out-
put (INTOSC) for 8 MHz (see Table 22-6). However,
this frequency may drift as V
changes and this directly affects the asynchronous
baud rate. Two methods may be used to adjust the
baud rate clock, but both require a reference clock
source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output back to 8 MHz.
Adjusting the value in the OSCTUNE register allows for
fine resolution changes to the system clock source (see
Section 3.6 “INTOSC Frequency Drift” for more
information).
The other method adjusts the value in the Baud Rate
Generator (BRG). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
Asynchronous Operation in Power
Managed Modes
PIC18F1220/1320
DD
DS39605C-page 131
or temperature