PIC18F1320-I/SO Microchip Technology, PIC18F1320-I/SO Datasheet - Page 305

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: IC MCU FLASH 4KX16 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timing Diagrams
 2004 Microchip Technology Inc.
A/D Conversion ........................................................ 267
Asynchronous Reception ......................................... 144
Asynchronous Transmission .................................... 141
Asynchronous Transmission
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 145
Brown-out Reset (BOR) ........................................... 262
Capture/Compare/PWM (All CCP Modules) ............ 264
CLKO and I/O .......................................................... 261
Clock/Instruction Cycle .............................................. 45
EUSART Synchronous Receive
EUSART SynchronousTransmission
External Clock (All Modes Except PLL) ................... 259
Fail-Safe Clock Monitor ............................................ 183
Low-Voltage Detect .................................................. 168
Low-Voltage Detect Characteristics ......................... 255
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 147
Slow Rise Time (MCLR Tied to V
Synchronous Reception
Synchronous Transmission ...................................... 148
Synchronous Transmission
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 263
Transition for Entry to SEC_IDLE Mode .................... 24
Transition for Entry to SEC_RUN Mode .................... 26
Transition for Entry to Sleep Mode ............................ 22
(Back to Back) .................................................. 142
Normal Operation ............................................. 145
(Master/Slave) .................................................. 266
(Master/Slave) .................................................. 265
Auto-Restart Disabled) ..................................... 128
Auto-Restart Enabled) ..................................... 128
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 262
V
(Master Mode, SREN) ...................................... 150
(Through TXEN) ............................................... 149
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
Rise > T
PWRT
DD
DD
) ............................................ 40
) ........................................... 40
, V
DD
DD
DD
), Case 1 ....................... 39
), Case 2 ....................... 39
Rise T
DD
,
PWRT
) .............. 39
Timing Diagrams and Specifications ............................... 259
Top-of-Stack Access .......................................................... 42
TSTFSZ ........................................................................... 231
Two-Speed Start-up ..................................................171, 181
Two-Word Instructions ....................................................... 46
TXSTA Register
W
Watchdog Timer (WDT) ............................................171, 180
WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 231
XORWF ........................................................................... 232
Transition for Two-Speed Start-up
Transition for Wake from PRI_IDLE Mode ................ 23
Transition for Wake from RC_RUN Mode
Transition for Wake from SEC_RUN Mode
Transition for Wake from Sleep (HSPLL) .................. 22
Transition to PRI_IDLE Mode .................................... 23
Transition to RC_IDLE Mode ..................................... 25
Transition to RC_RUN Mode ..................................... 27
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 261
EUSART Synchronous Receive
EUSART Synchronous Transmission
External Clock Requirements .................................. 259
Internal RC Accuracy ............................................... 260
PLL Clock, HS/HSPLL Mode
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
Example Cases .......................................................... 46
BRGH Bit ................................................................. 135
Associated Registers ............................................... 181
Control Register ....................................................... 180
During Oscillator Failure .......................................... 182
Programming Considerations .................................. 180
(INTOSC to HSPLL) ........................................ 181
(RC_RUN to PRI_RUN) .................................... 25
(HSPLL) ............................................................. 24
(All CCP Modules) ........................................... 265
Requirements .................................................. 266
Requirements .................................................. 265
(V
Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 263
Requirements .................................................. 264
PIC18F1220/1320
DD
= 4.2V to 5.5V) ........................................ 260
DS39605C-page 303