PIC18F1320-I/SO Microchip Technology, PIC18F1320-I/SO Datasheet - Page 29

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: IC MCU FLASH 4KX16 A/D 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA12XP080 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.4.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode pro-
vides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive, or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either of the INTIO1 or INTIO2 oscillators), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to and exit
from RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.
This mode is entered by clearing the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.
The IRCF bits may be modified at any time to immedi-
ately change the system clock speed. Executing a
SLEEP instruction is not required to select a new clock
frequency from the INTOSC multiplexer.
FIGURE 3-10:
 2004 Microchip Technology Inc.
Peripheral
Program
Counter
INTRC
OSC1
Clock
Clock
CPU
RC_RUN MODE
Q4
Q1
Q2
PC
Q3
TIMING TRANSITION TO RC_RUN MODE
Q4
Q1
1
2
3
Clock Transition
4
5
PC + 2
6
If the IRCF bits are all clear, the INTOSC output is not
enabled and the IOFS bit will remain clear; there will be
no indication of the current clock source. The INTRC
source is providing the system clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable. Clocks to
the system continue while the INTOSC source
stabilizes, in approximately 1 ms.
If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed and the
INTOSC source was already stable, the IOFS bit will
remain set.
When a wake event occurs, the system continues to be
clocked from the INTOSC multiplexer while the primary
clock is started. When the primary clock becomes
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is cleared, the OSTS bit is set and the primary
clock is providing the system clock. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
7
Note:
8
PIC18F1220/1320
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
DD
Q2
/F
OSC
Q3
specifications are violated.
Q4
DD
Q1
is less than 3V, it is
PC + 4
DS39605C-page 27
Q2
Q3
DD
.