MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 139

• Manufacturer Part Number: MC68HC908JB8JPE
• Description: IC MCU FLASH 8BIT 8K 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

9.8.2 USB Interrupt Register 0
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Address:
EOPIE — End-of-Packet Detect Interrupt Enable
SUSPND — USB Suspend Bit
TXD2IE — Endpoint 2 Transmit Interrupt Enable
Reset:
Read:
Write:
This read/write bit enables the USB to generate CPU interrupt
requests when the EOPF bit becomes set. Reset clears the EOPIE
bit.
To save power, this read/write bit should be set by the software if a
3ms constant idle state is detected on the USB bus. Setting this bit
puts the transceiver into a power-saving mode. The RESUMF flag
must be cleared before setting SUSPND. Software must clear this bit
after the resume flag (RESUMF) is set while this resume interrupt flag
is serviced.
This read/write bit enables the transmit endpoint 2 to generate CPU
interrupt requests when the TXD2F bit becomes set. Reset clears the
TXD2IE bit.
1 = End-of-packet sequence detection can generate a CPU
0 = End-of-packet sequence detection cannot generate a CPU
1 = Transmit endpoint 2 can generate a CPU interrupt request
0 = Transmit endpoint 2 cannot generate a CPU interrupt request
EOPIE
$0039
Bit 7
Universal Serial Bus Module (USB)
interrupt request
interrupt request
0
Figure 9-16. USB Interrupt Register 0 (UIR0)
SUSPND
= Unimplemented
6
0
TXD2IE
5
0
RXD2IE
4
0
TXD1IE
Universal Serial Bus Module (USB)
3
0
2
0
0
TXD0IE
1
0
Technical Data
I/O Registers
RXD0IE
Bit 0
0
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