MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 238

• Manufacturer Part Number: MC68HC908JB8JPE
• Description: IC MCU FLASH 8BIT 8K 20-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB8JPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: HC08
• No. Of I/o's: 13
• Ram Memory Size: 256Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Computer Operating Properly (COP)
15.3 Functional Description
Technical Data
238
NOTE:
1. See SIM section for more details.
INTERNAL RESET SOURCES
(COPRS FROM CONFIG)
RESET VECTOR FETCH
COPD (FROM CONFIG)
COPEN (FROM SIM)
COPCTL WRITE
COPCTL WRITE
COP RATE SEL
OSCXCLK
RESET
Figure 15-1
The COP counter is a free-running 6-bit counter preceded by a 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2
COP rate select bit, COPRS in the configuration register. With a 2
OSCXCLK cycle overflow option (COPRS = 0), a 12MHz OSCXCLK
clock (6MHz crystal) gives a COP timeout period of 21.84 ms. Writing
any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM
counter.
(1)
18
– 2
Figure 15-1. COP Block Diagram
4
or 2
Computer Operating Properly (COP)
COP MODULE
COP CLOCK
12-BIT SIM COUNTER
13
shows the structure of the COP module.
– 2
COP COUNTER
4
6-BIT COP COUNTER
CLEAR
OSCXCLK cycles, depending on the state of the
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
SIM
RESET STATUS REGISTER
SIM RESET CIRCUIT
Freescale Semiconductor
18
– 2
4