MC68HC908JB8JPE Freescale Semiconductor, MC68HC908JB8JPE Datasheet - Page 41

IC MCU FLASH 8BIT 8K 20-DIP

MC68HC908JB8JPE

Manufacturer Part Number
MC68HC908JB8JPE
Description
IC MCU FLASH 8BIT 8K 20-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908JB8JPE

Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
HC08
No. Of I/o's
13
Ram Memory Size
256Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
USB
Rohs Compliant
Yes
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
2.3 I/O Section
2.4 Monitor ROM
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Addresses $0000–$003F, shown in
control, status, and data registers. Additional I/O registers have these
addresses:
The 512 bytes at addresses $FC00–$FDFF and 464 bytes at addresses
$FE10–$FFDF are reserved ROM addresses that contain the
instructions for the monitor functions. (See
(MON).)
$FE00; break status register, BSR
$FE01; reset status register, RSR
$FE02; reserved
$FE03; break flag control register, BFCR
$FE04; interrupt status register 1, INT1
$FE05; reserved
$FE06; reserved
$FE07; reserved
$FE08; FLASH control register, FLCR
$FE09; FLASH block protect register, FLBPR
$FE0A; reserved
$FE0B; reserved
$FE0C; break Address Register High, BRKH
$FE0D; break Address Register Low, BRKL
$FE0E; break status and control register, BRKSCR
$FFFF; COP control register, COPCTL
Memory Map
Figure
Section 10. Monitor ROM
2-2, contain most of the
Technical Data
Memory Map
I/O Section
41

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