C8051F902-GU Silicon Laboratories Inc, C8051F902-GU Datasheet - Page 146

• Manufacturer Part Number: C8051F902-GU
• Description: IC MCU 8BIT 8KB FLASH 24QSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GU

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QSOP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1849-5

C8051F91x-C8051F90x
14.4. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. The system clock source must be set to the low power internal oscillator or the preci-
sion oscillator prior to entering suspend mode. All digital logic (timers, communication peripherals, inter-
rupts, CPU, etc.) stops functioning until one of the enabled wake-up sources occurs.
The following wake-up sources can be configured to wake the device from suspend mode:




Note: Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the PMU0CF wake-
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-
up was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 kW
pullup resistor to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VBAT pin (see Figure 14.1). Power to most digital logic on the
chip is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain pow-
ered in two-cell mode and lose their supply in one-cell mode because the dc-dc converter is disabled. In
two-cell mode, only the Comparators remain functional when the device enters sleep mode. All other ana-
log peripherals (ADC0, IREF0, External Oscillator, etc.) should be disabled prior to entering sleep mode.
The system clock source must be set to the low power internal oscillator or the precision oscillator prior to
entering sleep mode.
Note: When exiting sleep mode, 4 NOP instructions should be located immediately after the write to PMU0CF
Note: If the average active time (between successive entries into Sleep Mode) is less than 1 ms, peripherals
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode. In one-cell
mode, the VDD/DC+ supply will drop to the level of VBAT, which will reduce the output high-voltage level
and the source and sink current drive capability.
GPIO pins configured as digital inputs can be used during sleep mode as wakeup sources using the port
match feature. In two-cell mode, they will maintain the same input level specs in sleep mode as they have
in normal mode. In one-cell mode, the VDD supply will drop to the level of VBAT, which will lower the
switching threshold and increase the propagation delay.
C8051F912 and C8051F902 devices support a wakeup request for external devices. Upon exit from sleep
mode, the wake-up request signal is driven high, allowing other devices in the system to wake up from
their low power modes. An example of a system that may benefit from this function is one that uses a high-
power dc-dc converter (>65 mW of output power). The dc-dc converter may be disabled when the system
is asleep, and can be awoken by the wake-up request signal from the MCU. The wakeup request signal is
high when the MCU is awake and low when the MCU is asleep.
146
SmaRTClock Oscillator Fail
SmaRTClock Alarm
Port Match Event
Comparator0 Rising Edge
up flags. All flags will read back a value of '0' during the first two system clocks following a wake-up from
suspend mode.
that placed the device in sleep mode.
that may cause a wake-up from Sleep Mode (SmaRTClock, Port Match, and Comparator0) or are
enabled or configured in a way which may cause the wake-up flag to be set should be selected as
wake-up sources. If these peripherals are not selected as wake-up sources, then it is recommended to
bypass the Flash one-shot (FLSCL.6=1) before entering into Sleep Mode.
Rev. 1.0