C8051F902-GU Silicon Laboratories Inc, C8051F902-GU Datasheet - Page 178

• Manufacturer Part Number: C8051F902-GU
• Description: IC MCU 8BIT 8KB FLASH 24QSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GU

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QSOP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1849-5

C8051F91x-C8051F90x
SFR Definition 18.2. RSTSRC: Reset Source
SFR Page = 0x0; SFR Address = 0xEF.
178
Notes:
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD/DC+ Supply Monitor is stabilized may generate a system reset.
WDTRSF Watchdog Timer Reset Flag. N/A
MCDRSF Missing Clock Detector
FERROR Flash Error Reset Flag.
RTC0RE SmaRTClock Reset Enable
C0RSEF Comparator0 Reset Enable
PINRSF
SWRSF
PORSF
Name
RTC0RE
Varies
R/W
7
and Flag
and Flag.
Software Reset Force and
Flag.
(MCD) Enable and Flag.
Power-On / Power-Fail
Reset Flag, and Power-Fail
Reset Enable.
HW Pin Reset Flag.
FERROR
Varies
R
6
Description
C0RSEF
Varies
R/W
5
SWRSF
Varies
R/W
Rev. 1.0
0: Disable SmaRTClock
as a reset source.
1: Enable SmaRTClock as
a reset source.
N/A
0: Disable Comparator0 as
a reset source.
1: Enable Comparator0 as
a reset source.
Writing a 1 forces a sys-
tem reset.
0: Disable the MCD.
1: Enable the MCD.
The MCD triggers a reset
if a missing clock condition
is detected.
0: Disable the VDD/DC+
Supply Monitor as a reset
source.
1: Enable the VDD/DC+
Supply Monitor as a reset
source.
N/A
4
3
WDTRSF
Varies
Write
R
3
MCDRSF
Varies
R/W
2
Set to 1 if SmaRTClock
alarm or oscillator fail
caused the last reset.
Set to 1 if Flash
read/write/erase error
caused the last reset.
Set to 1 if Comparator0
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
Set to 1 anytime a power-
on or V
occurs.
Set to 1 if RST pin caused
the last reset.
PORSF
Varies
R/W
DD
2
1
Read
monitor reset
PINRSF
Varies
R
0