C8051F902-GU Silicon Laboratories Inc, C8051F902-GU Datasheet - Page 52

• Manufacturer Part Number: C8051F902-GU
• Description: IC MCU 8BIT 8KB FLASH 24QSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F902-GU

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 15x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 768 B
• Interface Type: UART
• Maximum Clock Frequency: 25 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F912DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Package: 24QSOP
• Device Core: 8051
• Family Name: C8051F90x
• Maximum Speed: 25 MHz
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1849-5

Table 4.4. Reset Electrical Characteristics
V
C8051F91x-C8051F90x
52
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
VDD/DC+ Monitor
Threshold (V
VBAT Ramp Time for
Power On
VBAT Monitor Threshold
(V
Missing Clock Detector
Timeout
Minimum System Clock w/
Missing Clock Detector
Enabled
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
V
V
Current
*Note:
DD
DD
DD
POR
= 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Monitor Turn-on Time
Monitor Supply 
)
Blue
Parameter
indicates a feature only available on ‘F912 and ‘F902 devices.
RST
)
Recovery from Brownout (VBAT Rising)
Time from last system clock rising edge
System clock frequency which triggers
Delay between release of any reset
Brownout Condition (VBAT Falling)
a missing clock detector timeout
(all power modes except Sleep)
Initial Power-On (VBAT Rising)
execution at location 0x0000
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
VBAT Ramp from 0–0.9 V
V
V
V
V
source and code
to reset initiation
DD
DD
DD
DD
Early Warning
Early Warning
Reset Trigger
I
OL
Conditions
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 1.4 mA,
Rev. 1.0
V
0.7 x V
DD
Min
100
1.8
1.7
0.9
0.7
15
—
—
—
—
—
—
—
—
—
—
—
—
– 0.6
DD
1.85
1.75
0.75
0.95
Typ
525
300
1.0
0.8
—
—
—
—
—
20
—
10
—
10
4
2
0.3 x V
1000
Max
0.6
0.6
1.9
1.8
1.1
0.9
35
10
—
—
—
—
—
—
—
—
—
3
DD
Units
kHz
µA
ms
µA
µs
µs
µs
ns
V
V
V
V
V
V
V