MCIMX512CJM6C Freescale Semiconductor, MCIMX512CJM6C Datasheet - Page 70

• Manufacturer Part Number: MCIMX512CJM6C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX512CJM6C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
1
2
4.7
The following sections provide information on external peripheral interfaces.
70
DDR24
DDR25
DDR26
Test conditions are: Capacitance of 15 pF for DDR contacts. The recommended drive strength is Medium for SDCLK and High
for address and controls
SDCLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value
and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and
SDCLK_B.
ID
DQS (input)
SDCLK_B
DQ (input)
SDCLK
DQS - DQ Skew (defines the Data valid window in read cycles related to
DQS).
DQS DQ in HOLD time from DQS
DQS output access time from SDCLK posedge
External Peripheral Interfaces
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Figure 36. DDR2 SDRAM DQ versus DQS and SDCLK Read Cycle
DDR26
DDR24
Table 63. DDR2 SDRAM Read Cycle
Parameter
DATA
DATA
DDR25
DATA
DATA
DATA
1
Symbol
t
t
DQSCK
DQSQ
t
QH
DATA
SDCLK = 200 MHz
–0.5
Min
1.8
—
Freescale Semiconductor
DATA
Max
0.35
0.5
—
DATA
2
Unit
ns
ns
ns