MCIMX512CJM6C Freescale Semiconductor, MCIMX512CJM6C Datasheet - Page 94

• Manufacturer Part Number: MCIMX512CJM6C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX512CJM6C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
4.7.8.6
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of
the interface is described in
94
2
3
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Display interface clock down time
Display interface clock up time
Interface to a TV Encoder
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•
•
•
•
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i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
The frequency of the clock DISP_CLK is 27 MHz (within 10%)
The HSYNC, VSYNC signals are active low.
The DRDY signal is shown as active high.
The transition to the next row is marked by the negative edge of the
HSYNC signal. It remains low for a single clock cycle
The transition to the next field/frame is marked by the negative edge of
the VSYNC signal. It remains low for at least one clock cycles
—
of VSYNC and HSYNC coincide.
—
coincide.
The active intervals—during which data is transferred—are marked by
the HSYNC signal being high.
At a transition to an odd field (of the next frame), the negative edges
At a transition is to an even field (of the same frame), they do not
Figure
Tdicd
Tdicu
56.
=
=
1
-- - T diclk
2
⎛
⎝
1
-- - T diclk
2
⎛
⎝
×
ceil
×
NOTE
ceil
2
------------------------------------------------------------ -
×
2
-------------------------------------------------- -
DI_CLK_PERIOD
DI_CLK_PERIOD
DISP_CLK_DOWN
×
DISP_CLK_UP
⎞
⎠
⎞
⎠
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