LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 119

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
SMSC LAN9313/LAN9313i
8.4.1
INSTRUCTION
WRITE_DEC
READ_DEC
WRITE_INC
READ_INC
WRITE
READ
The SPI instructions supported by the LAN9313/LAN9313i are listed in
instructions are must not be used.
SPI Read Sequence
The SPI slave interface of the LAN9313/LAN9313i is selected for reads by first bringing nSCS low.
The SI pin should then driven with an 8-bit read instruction, followed by the 8-bit address. On the falling
clock edge which follows the rising edge of the last address bit, the SO output is driven starting with
the msb of the selected register. The remaining register bits are shifted out on subsequent falling clock
edges.
Multiple reads are performed by continuing the clock pulses while nSCS is low. Depending on the
instruction (as shown in
Maintaining a fixed internal address is useful for register polling. For auto-incrementing instructions,
once the internal address reaches its maximum, it rolls over to 0. For auto-decrementing instructions,
once the internal address reaches 0, it rolls over to its maximum.
The nSCS input is brought high to conclude the cycle. The SO output pin is three-stated at this time.
Since data is read serially, register values are latched (registered) at the beginning of each 32-bit read
to prevent the host from reading an intermediate value. The latching occurs multiple times in a multiple
read sequence. In addition, any register that is affected by a read operation (e.g. a clear on read bit)
is not cleared until after all 32-bits are output. In the event that 32-bits are not read when the nSCS is
returned high, the read is considered invalid and the register is not affected. Multiple registers may be
cleared in a multiple read cycle, each one being cleared as it is read.
SPI reads from unused register addresses return as all zeros.
0000 0011
0000 1011
0000 0010
0000 0110
0000 1010
0000 0111
FORMAT
Table 8.10 Supported SPI Instructions
Table
Write register at the specified address.
Read register at the specified address.
Multiple reads maintain the same address.
Read register(s) starting at the specified address.
Multiple reads auto-increment address.
Read register(s) starting at the specified address.
Multiple reads auto-decrement address.
Multiple writes maintain the same address.
Write register(s) starting at the specified address.
Multiple writes auto-increment address.
Write register(s) starting at the specified address.
Multiple writes auto-decrement address.
8.10), the internal address is incremented, decremented, or maintained.
DATASHEET
119
DESCRIPTION
Table
Revision 1.7 (06-29-10)
8.10. Unsupported