LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 266

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
13.3.1.3
BITS
31:9
8:7
4:3
6
5
2
1
0
RESERVED
RESERVED
Note:
Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of switch fabric interrupts due to the
Buffer Manager via the
(BM_IPR). The status bits in the SW_IPR register are not affected.
Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of switch fabric interrupts due to the
Switch Engine via the
The status bits in the SW_IPR register are not affected.
RESERVED
Note:
Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of switch fabric interrupts due to the Port
2 MAC via the MAC_IPR_2 register (see
The status bits in the SW_IPR register are not affected.
Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of switch fabric interrupts due to the Port
1 MAC via the MAC_IPR_1 register (see
The status bits in the SW_IPR register are not affected.
Port 0 MAC Interrupt Mask (MAC_MII)
When set, prevents the generation of switch fabric interrupts due to the Port
0 MAC via the MAC_IPR_MII register (see
The status bits in the SW_IPR register are not affected.
Switch Global Interrupt Mask Register (SW_IMR)
This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch
related interrupts in the
register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will
unmask the interrupt. When an unmasked switch fabric interrupt is generated in the
Interrupt Pending Register
Status Register
These bits must be written as 11b
These bits must be written as 11b
Register #:
(INT_STS). Refer to
Switch Engine Interrupt Pending Register
Buffer Manager Interrupt Pending Register
Switch Global Interrupt Pending Register (SW_IPR)
0004h
DESCRIPTION
(SW_IPR), the interrupt will trigger the SWITCH_INT bit in the
DATASHEET
Chapter 5, "System Interrupts," on page 52
Section 13.3.2.44, on page
Section 13.3.2.44, on page
Section 13.3.2.44, on page
266
Size:
(SWE_IPR).
Three Port 10/100 Managed Ethernet Switch with MII
32 bits
311).
311).
311).
TYPE
may be masked via this
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMSC LAN9313/LAN9313i
RO
for more information.
Switch Global
DEFAULT
11b
11b
Datasheet
1b
1b
1b
1b
1b
Interrupt
-