LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 42

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.7 (06-29-10)
4.2.1
4.2.1.1
RESET SOURCE
Digital Reset
Virtual PHY
Port 2 PHY
Port 1 PHY
nRST Pin
Chip-Level Resets
A chip-level reset event activates all internal resets, effectively resetting the entire LAN9313/LAN9313i.
Configuration straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A
chip-level reset is initiated by assertion of any of the following input events:
Chip-level reset/configuration completion can be determined by first polling the
Register
Once the returned data is the correct byte ordering value, the serial interface resets have completed.
The completion of the entire chip-level reset must then be determined by polling the READY bit of the
Hardware Configuration Register (HW_CFG)
reset has completed and the device is ready to be accessed.
With the exception of the
(BYTE_TEST), and
forbidden while the READY bit is cleared. Writes to any address are invalid until the READY bit is set.
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the LAN9313/LAN9313i, or if the power
is removed and reapplied to the LAN9313/LAN9313i. This event resets all circuitry within the device.
Configuration straps are latched, and the EEPROM Loader is run as a result of this reset.
A POR reset typically takes approximately 23mS, plus additional time (91uS for I
Microwire) per byte of data loaded from the EEPROM via the EEPROM Loader. A full EEPROM load
(64KB for I
80mS for Microwire EEPROM.
POR
Power-On Reset (POR)
nRST Pin Reset
Table 4.1 Reset Sources and Affected LAN9313/LAN9313i Circuitry
(BYTE_TEST). The returned data will be invalid until the serial interface resets are complete.
2
C, 2KB for Microwire) will complete in approximately 6.0 seconds for I
X
X
X
X
X
X
Reset Control Register
Hardware Configuration Register
X
X
X
DATASHEET
X
X
X
X
X
42
X
X
X
(RESET_CTL), read access to any internal resources is
until it is set. When set, the READY bit indicates that the
X
X
X
X
X
X
Three Port 10/100 Managed Ethernet Switch with MII
(HW_CFG),
X
X
X
X
X
X
Byte Order Test Register
SMSC LAN9313/LAN9313i
X
X
X
2
C EEPROM, and
Byte Order Test
2
C, 28uS for
X
X
Datasheet
X
X
X