LAN9313I-NZW SMSC, LAN9313I-NZW Datasheet - Page 125

• Manufacturer Part Number: LAN9313I-NZW
• Description: Ethernet ICs Three Port 10/100 Ethernet Switch
• Manufacturer: SMSC
• Type: Three Port Managed Ethernet Switchr

Specifications of LAN9313I-NZW

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 155 mA, 270 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Three Port 10/100 Managed Ethernet Switch with MII
Datasheet
Chapter 9 MII Management
SMSC LAN9313/LAN9313i
9.1
9.2
WRITE
READ
PREAMBLE
32 1’s
32 1’s
This chapter details the MII management functionality provided by the LAN9313/LAN9313i, which
includes the
The
and allows CPU access to all system CSRs. The
the internal PHYs and optional external PHY, dependant on the management mode. The PMI
implements the IEEE 802.3 management protocol. The
connections of the MII data path and MII management path based on the selected mode of the device.
The SMI slave controller uses the same pins and protocol as the IEEE 802.3 MII management function,
and differs only in that SMI provides access to all internal registers by using a non-standard extended
addressing map. The SMI protocol co-exists with the MII management protocol by using the upper half
of the PHY address space (16 through 31). All direct and indirect registers of the LAN9313/LAN9313i
can be accessed. The SMI management mode is selected when the mngt_mode_strap[1:0] inputs are
set to 01b. A list of management modes and their configuration settings are discussed in
"Modes of Operation," on page
The MII management protocol is limited to 16-bit data accesses. The protocol is also limited to 5 PHY
address bits and 5 register address bits. The SMI frame format can be seen in
LAN9313/LAN9313i uses the PHY Address field bits 3:0 as the system register address bits 9:6, and
the Register Address field as the system register address bits 5:1. Therefore, Register Address field
bit 0 is used as the upper/lower word select. The LAN9313/LAN9313i requires two back-to-back
accesses to each register (with alternate settings of Register Address field bit 0) which are combined
to form a 32-bit access. The access may be performed in any order.
Note: When accessing the LAN9313/LAN9313i, the pair of cycles must be atomic. In this case, the
Input data on the MDIO pin is sampled on the rising edge of the MDC input clock. Output data is
sourced on the MDIO pin with the rising edge of the clock. The MDIO pin is three-stated unless actively
driving read data.
A read or a write is performed using the frame format shown in
transferred msb first. Data bytes are transferred little endian. When Register Address bit 0 is 1, bytes
3 & 2 are selected with byte 3 occurring first. When Register Address bit 0 is 0, bytes 1 & 0 are
selected with byte 1 occurring first.
Functional Overview
SMI Slave Controller
SMI Slave Controller
first host SMI cycle is performed to the low/high word and the second host SMI cycle is
performed to the high/low word, forming a 32-bit transaction with no cycles to the
LAN9313/LAN9313i in between. With the exception of Register Address field bit 0, all address
and control bits must be the same for both 16-bit cycles of a 32-bit transaction.
START
SMI Slave
01
01
CODE
OP
10
01
Controller,
is used for CPU management of the LAN9313/LAN9313i via the MII pins,
Table 9.1 SMI Frame Format
ADDRESS
Note 9.1
23.
1AAAA
1AAAA
PHY
9876
9876
DATASHEET
PHY Management Interface
125
REGISTER
ADDRESS
Note 9.1
AAAAA
AAAAA
54321
54321
PHY Management Interface (PMI)
AROUND
Note 9.2
MII Mode Multiplexer
TURN-
TIME
Z0
10
Table
(PMI), and the
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
9.1. All addresses and data are
5432109876543210
5432109876543210
1111110000000000
1111110000000000
DATA
MII Mode
is used to direct the
Revision 1.7 (06-29-10)
is used to access
Table
Section 2.3,
Multiplexer.
9.1. The
IDLE
Note
9.3
Z
Z