XC2V2000-4FGG676C Xilinx Inc, XC2V2000-4FGG676C Datasheet - Page 73

• Manufacturer Part Number: XC2V2000-4FGG676C
• Description: FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V2000-4FGG676C

• Package: 676FBGA
• Family Name: Virtex-II™
• Device Logic Units: 24192
• Device System Gates: 2000000
• Number Of Registers: 21504
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 456
• Ram Bits: 1032192
• Number Of Labs/clbs: 2688
• Total Ram Bits: 1032192
• Number Of I /o: 456
• Number Of Gates: 2000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1351

Table 27: Enhanced Pipelined Multiplier Switching Characteristics
DS031-3 (v3.5) November 5, 2007
Product Specification
Data Inputs
Clock Enable
Reset
Clock to Output Pin
Clock to Pin 35
Clock to Pin 34
Clock to Pin 33
Clock to Pin 32
Clock to Pin 31
Clock to Pin 30
Clock to Pin 29
Clock to Pin 28
Clock to Pin 27
Clock to Pin 26
Clock to Pin 25
Clock to Pin 24
Clock to Pin 23
Clock to Pin 22
Clock to Pin 21
Clock to Pin 20
Clock to Pin 19
Clock to Pin 18
Clock to Pin 17
Clock to Pin 16
Clock to Pin 15
Clock to Pin 14
Clock to Pin 13
Clock to Pin 12
Clock to Pin 11
Clock to Pin 10
Clock to Pin 9
Clock to Pin 8
Clock to Pin 7
Clock to Pin 6
Clock to Pin 5
Clock to Pin 4
Clock to Pin 3
Clock to Pin 2
Clock to Pin 1
Clock to Pin 0
Setup and Hold Times Before/After Clock
R
Description
T
T
MULIDCK_RST
MULIDCK_CE
T
MULIDCK
www.xilinx.com
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
MULTCK1_P35
MULTCK1_P34
MULTCK1_P33
MULTCK1_P32
MULTCK1_P31
MULTCK1_P30
MULTCK1_P29
MULTCK1_P28
MULTCK1_P27
MULTCK1_P26
MULTCK1_P25
MULTCK1_P24
MULTCK1_P23
MULTCK1_P22
MULTCK1_P21
MULTCK1_P20
MULTCK1_P19
MULTCK1_P18
MULTCK1_P17
MULTCK1_P16
MULTCK1_P15
MULTCK1_P14
MULTCK1_P13
MULTCK1_P12
MULTCK1_P11
MULTCK1_P10
MULTCK1_P9
MULTCK1_P8
MULTCK1_P7
MULTCK1_P6
MULTCK1_P5
MULTCK1_P4
MULTCK1_P3
MULTCK1_P2
MULTCK1_P1
MULTCK1_P0
Symbol
Virtex-II Platform FPGAs: DC and Switching Characteristics
/T
/T
/T
MULCKID
MULCKID_CE
MULCKID_RST
3.00/0.00
0.72/0.00
0.72/0.00
3.05
2.95
2.85
2.76
2.66
2.56
2.47
2.37
2.27
2.17
2.08
1.98
1.88
1.79
1.69
1.59
1.50
1.40
1.30
1.20
1.11
1.01
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
0.91
-6
Speed Grade
3.45/0.00
0.80/0.00
0.80/0.00
3.25
3.14
3.04
2.93
2.82
2.72
2.61
2.50
2.40
2.29
2.18
2.07
1.97
1.86
1.75
1.65
1.54
1.43
1.33
1.22
1.11
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
-5
3.89/0.00
0.86/0.00
0.86/0.00
3.74
3.61
3.49
3.37
3.25
3.12
3.00
2.88
2.75
2.63
2.51
2.38
2.26
2.14
2.02
1.89
1.77
1.65
1.52
1.40
1.28
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
1.15
-4
Module 3 of 4
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Units
25