XC2V2000-4FGG676C Xilinx Inc, XC2V2000-4FGG676C Datasheet - Page 86

• Manufacturer Part Number: XC2V2000-4FGG676C
• Description: FPGA Virtex-II™ Family 2M Gates 24192 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 676-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V2000-4FGG676C

• Package: 676FBGA
• Family Name: Virtex-II™
• Device Logic Units: 24192
• Device System Gates: 2000000
• Number Of Registers: 21504
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 456
• Ram Bits: 1032192
• Number Of Labs/clbs: 2688
• Total Ram Bits: 1032192
• Number Of I /o: 456
• Number Of Gates: 2000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1351

Miscellaneous Timing Parameters
Table 42: Miscellaneous Timing Parameters
Frequency Synthesis
Table 43: Frequency Synthesis
Parameter Cross Reference
Table 44: Parameter Cross Reference
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. Specification also applies to PSCLK.
Time Required to Achieve LOCK
Using DLL outputs
Using CLKFX outputs
Additional lock time with
fine-phase shifting
Fine-Phase Shifting
Absolute shifting range
Delay Lines
Tap delay resolution
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
Description
R
(1)
Libraries Guide
CLKFX_MULTIPLY
CLKFX_DIVIDE
LOCK_DLL
LOCK_DLL_60
LOCK_DLL_50_60
LOCK_DLL_40_50
LOCK_DLL_30_40
LOCK_DLL_24_30
LOCK_FX_MIN
LOCK_FX_MAX
LOCK_DLL_FINE_SHIFT
FINE_SHIFT_RANGE
DCM_TAP_MIN
DCM_TAP_MAX
Attribute
Symbol
www.xilinx.com
Virtex-II Platform FPGAs: DC and Switching Characteristics
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
Constraints
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
24 - 30 MHz
> 60MHz
F
CLKIN
Min
2
1
120.0
20.0
25.0
50.0
90.0
10.0
10.0
50.0
10.0
30.0
60.0
-6
Data Sheet
Speed Grade
120.0
20.0
25.0
50.0
90.0
10.0
10.0
50.0
10.0
30.0
60.0
-5
Max
120.0
20.0
25.0
50.0
90.0
10.0
10.0
50.0
10.0
30.0
60.0
32
32
-4
Module 3 of 4
Units
ms
ms
μs
μs
μs
μs
μs
μs
ns
ps
ps
38