DP83846AVHG63SN National Semiconductor, DP83846AVHG63SN Datasheet
DP83846AVHG63SN
Specifications of DP83846AVHG63SN
Related parts for DP83846AVHG63SN
DP83846AVHG63SN Summary of contents
Page 1
... Network Interface Cards PCMCIA Cards System Diagram Ethernet MAC MII ©2002 National Semiconductor Corporation Features IEEE 802.3 ENDEC, 10BASE-T transceivers and filters IEEE 802.3u PCS, 100BASE-TX transceivers and filters IEEE 802.3 compliant Auto-Negotiation Output edge rate control eliminates external filtering for ...
Page 2
... OUTPUT DRIVER LED DRIVERS LEDS TD± Figure 1. Block Diagram of the 10/100 DSP based core. MII SERIAL MANAGEMENT MII INTERFACE/CONTROL RX_CLK TX_CLK REGISTERS MII PHY ADDRESS AUTO NEGOTIATION BASIC MODE CONTROL PCS CONTROL 10BASE-T 100BASE-TX AUTO-NEGOTIATION STATE MACHINE CLOCK GENERATION SYSTEM CLOCK REFERENCE ...
Page 3
... Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 Extended Registers . . . . . . . . . . . . . . . . . . . . . . . 37 6.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 44 6.1 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2 PGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 MII Serial Management Timing . . . . . . . . . . . . . . 47 6.4 100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.5 10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.6 Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.7 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3 www.national.com ...
Page 4
... RESERVED 74 RESERVED 75 SUB_GND 76 RESERVED 77 RESERVED 78 SUB_GND 79 RESERVED 80 DP83846A DSPHYTER Plastic Quad Flat Pack (LQFP) Order Number DP83846AVHG NS Package Number VHG-80A 4 RXD_1 40 RXD_2 39 RXD_3 38 MDC 37 MDIO 36 IO_VDD 35 IO_GND 34 LED_DPLX/PHYAD0 33 LED_COL/PHYAD1 32 LED_GDLNK/PHYAD2 31 LED_TX/PHYAD3 30 LED_RX/PHYAD4 29 LED_SPEED 28 AN_EN 27 AN_1 26 AN_0 25 CORE_VDD 24 CORE_GND 23 RESERVED 22 RESERVED 21 www.national.com ...
Page 5
... MHz with no minimum clock rate. 36 MANAGEMENT DATA I/O: Bi-directional management instruc- tion/data signal that may be sourced by the station management en- tity or the PHY. This pin requires a 1 CARRIER SENSE: Asserted high to indicate the presence of carrier due to receive or transmit activity in 10BASE-T or 100BASE-TX Half Duplex Modes, while in full duplex mode carrier sense is asserted to indicate the presence of carrier due only to receive activity ...
Page 6
Signal Name Type RXD[3] O, PU/PD 38, 39, 40, 41 RECEIVE DATA: Nibble wide receive data (synchronous to corre- RXD[2] RXD[1] RXD[0] RX_ER/PAUSE_EN RX_DV O 1.2 10 Mb/s and 100 Mb/s PMD Interface Signal Name Type TD+, ...
Page 7
... Vcc or GND. LQFP Pin # 33 PHY ADDRESS [4:0]: The DP83846A provides five PHY address pins, the state of which are latched into the PHYCTRL register at 32 system Hardware-Reset. 31 The DP83846A supports PHY Address strapping values 0 30 (< ...
Page 8
Signal Name Type AN_EN AN_1 AN_0 RX_ER/PAUSE_EN CRS/LED_CFG LQFP Pin # 27 Auto-Negotiation Enable: When high enables Auto-Negotiation with the capability set by ANO and AN1 pins. When low, puts ...
Page 9
Reset Signal Name Type RESET I 1.8 Power and Ground Pins Signal Name TTL/CMOS INPUT/OUTPUT SUPPLY IO_VDD 35, 43, 57, 65 IO_GND 34, 42, 53, 56, 64 INTERNAL SUPPLY PAIRS CORE_VDD 24, 49, 72 CORE_GND 23, 48, 73 ANALOG ...
Page 10
... TD+ 17 TD- 18 ANA_GND 19 SUB_GND 20 RESERVED 21 RESERVED 22 RESERVED 23 CORE_GND 24 CORE_VDD 25 AN_0 26 AN_1 27 AN_EN 28 LED_SPEED 29 LED_RX /PHYAD4 30 LED_TX /PHYAD3 31 LED_GDLNK/PHYAD2 32 LED_COL /PHYAD1 33 LED_FDPLX /PHYAD0 34 IO_GND 35 IO_VDD 36 MDIO 37 MDC 38 RXD_3 39 RXD_2 40 RXD_1 LQFP Pin # Pin Name 41 RXD_0 42 IO_GND 43 IO_VDD 44 RX_DV 45 RX_CLK 46 RX_ER/PAUSE_EN 47 RESERVED 48 CORE_GND ...
Page 11
... DP83846A. The AN0 and AN1 pins do not affect the contents of the BMCR and cannot be used by software to obtain status of the mode selected. Bits 1 & the PHYSTS register are only valid if Auto-Negotiation is disabled or after Auto-Negotiation is complete. The Auto- Negotiation protocol compares the contents of the ...
Page 12
... Refer to Section 3.1.4, PHY Address Sensing section for more details. The state of each of the PHYAD inputs latched into the PHYCTRL register bits [4:0] at system power-up/reset depends on whether a pull-up or pull-down resistor has been installed for each pin. For further detail relating to the ...
Page 13
... The LED_FDPLX pin indicates the Half or Full Duplex con- figuration of the port in both 10 Mb/s and 100 Mb/s opera- tion. Since this pin is also used as the PHY address strap option, the polarity of this indicator may be adjusted so that in the “active” (FULL DUPLEX selected) state it drives against the pullup/pulldown strap ...
Page 14
... BMCR register. In addition, the MII isolate mode can be selected by strapping in Physical Address 0. It should be noted that selecting Physical Address 0 via an MDIO write to PHYCTRL will not put the device in the MII isolate mode. When in the MII isolate mode, the DP83846A does not ...
Page 15
... The addressed DP83846A drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 3 shows the timing relationship between MDC and the MDIO as driven/received by the Sta- tion (STA) and the DP83846A (PHY) for a typical register read access. Table 4. Typical MDIO Frame Format Z ...
Page 16
... The DP83846A supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). Strapping PHY Address 0 puts the part into Isolate Mode. It should also be noted that selecting PHY Address 0 via an MDIO write to PHYC- TRL will not put the device in Isolate Mode; Address 0 must be strapped in. ...
Page 17
The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications where data conversion is not always required. The FROM PGM BP_4B5B BP_SCR 100BASE-TX Figure 5. 100BASE-TX Transmit Block Diagram 3.2.1 Code-group Encoding and Injection The ...
Page 18
... NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83846A uses the PHY_ID (pins PHYAD [4:0]) to set a unique seed value. 3.2.3 NRZ to NRZI Encoder After the transmit data stream has been serialized and ...
Page 19
Table 5. 4B5B Code-Group Encoding/Decoding Name PCS 5B Code-group DATA CODES IDLE AND CONTROL CODES INVALID CODES V ...
Page 20
The 100BASE-TX MLT-3 signal sourced by the TD com- mon driver output pins is slew rate controlled. This should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant transition times (3 ns < Tr < 5 ns). ...
Page 21
RX_CLK ÷5 BP_4B5B 4b/5b Decoder Code group BP_SCR DEscrambler CLOCK nrzi to nrz Clock decoder Recovery Module MLT-3 to Binary decoder Digital adaptive Equalization AGC InPUT BLW Compensation ADC rd Figure 8. Receive Block Diagram RXD[3:0] / RX_ER mux Serial ...
Page 22
Left uncompensated, events such as this can cause packet loss. 3.3.2 Signal Detect The signal detect function of the DP83846A is incorporated to meet the specifications mandated by the ANSI FDDI TP- PMD Standard as well ...
Page 23
... SQE is reported as a pulse on the COL signal of the MII. The SQE test is inhibited when the PHY is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the 10BTSCR register. 3.4.3 Carrier Sense Carrier Sense (CRS) may be asserted due to receive activ- ity once valid data is detected via the squelch function ...
Page 24
... The user is cautioned that if Auto Polarity Detection and Correction is disabled and inverted Polarity is detected but not corrected, the DsPHYTER may falsely report Good Link status and allow Transmission and Reception of inverted data recommended that Auto Polarity Detec- tion and Correction not be disabled during normal opera- tion ...
Page 25
ESD Protection Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures can be implemented during the manufacturing process to greatly reduce the occurrences ...
Page 26
... Crystal Oscillator Circuit The DsPHYTER supports an external CMOS level oscilla- tor source or a crystal resonator device external clock source is used, X1 should be tied to the clock source and X2 should be left floating. In either case, the clock source must MHz 0.005% (50 PPM) CMOS oscillator MHz (50 PPM), parallel load crystal resonator ...
Page 27
... RW Table 6. Register Map Tag BMCR Basic Mode Control Register BMSR Basic Mode Status Register PHYIDR1 PHY Identifier Register #1 PHYIDR2 PHY Identifier Register #2 ANAR Auto-Negotiation Advertisement Register ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page) ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page) ...
Page 28
... Addr Basic Mode Control Register 00h BMCR Basic Mode Status Register 01h BMSR PHY Identifier Register 1 02h PHYIDR1 PHY Identifier Register 2 03h PHYIDR2 Auto-Negotiation Advertisement Register 04h ANAR Auto-Negotiation Link Partner Ability Regis- 05h ANLPAR ter (Base Page) Auto-Negotiation Link Partner Ability Regis- ...
Page 29
Register Definition In the register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access SC — =Register sets on event occurrence and Self-Clears when event ends — RW/SC =Read Write access/Self Clearing bit — ...
Page 30
... Power Down 0, RW Power Down Power down Normal operation. Setting this bit powers down the PHY. Only the register block is enabled during a power down condition. 10 Isolate 0, RW Isolate Isolates the Port from the MII with the exception of the serial management. ...
Page 31
Table 8. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name Default 15 100BASE-T4 0, RO/P 14 100BASE-TX 1, RO/P Full Duplex 13 100BASE-TX 1, RO/P Half Duplex 12 10BASE-T 1, RO/P Full Duplex 11 10BASE-T 1, RO/P Half ...
Page 32
... The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83846A. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num- ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE assigned OUI is 080017h. ...
Page 33
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Nego- tiation. Table 11. Auto-Negotiation Advertisement Register (ANAR), address 0x04 Bit Bit Name RESERVED 13 RF 12:11 RESERVED ...
Page 34
This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto negotiation if Next-pages are supported. Table 12. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 Bit Bit ...
Page 35
Table 13. Auto-Negotiation Link Partner Ability Register (ANLPAR) Next Page, address 0x05 Bit Bit Name ACK ACK2 11 Toggle 10:0 CODE <000 0000 0000>, This register contains additional Local Device and Link Partner status ...
Page 36
This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 Bit Bit Name RESERVED ACK2 11 TOG_TX ...
Page 37
... Link Code Word Page Received: This is a duplicate of the Page Received bit in the ANER register, but this bit will not be cleared upon a read of the PHYSTS register new Link Code Word Page has been received. Cleared on read of the ANER (address 0x06, bit 1). ...
Page 38
... Auto-Negotiation is disabled and there is a valid link. Link Status: This bit is a duplicate of the Link Status bit in the BMSR register, except that it will no be cleared upon a read of the PHYSTS regis- ter Valid link established (for either 10 or 100 Mb/s operation Link not established. ...
Page 39
... Bit Name 15:8 RESERVED 7:0 FCSCNT[7:0] This counter provides information required to implement the “SymbolErrorDuringCarrier” attribute within the PHY man- aged object class of Clause 30 of the IEEE 802.3u specification. Table 18. Receiver Error Counter Register (RECR), address 0x15 Bit Bit Name 15:8 ...
Page 40
Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (Continued) Bit Bit Name Default 7 Unused 0,RO 6 RESERVED 5 FORCE_100_OK RESERVED 3 RESERVED 2 NRZI_BYPASS SCRAM_BYPASS DESCRAM_BYPA ...
Page 41
... Table 21. PHY Control Register (PHYCTRL), address 0x19 Bit Bit Name Default 15:12 Unused 11 PSR_15 BIST_STATUS 0, RO/LL 9 BIST_START BP_STRETCH PAUSE_STS 6 RESERVED 1, RO/P 5 LED_CNFG Strap, RW 4:0 PHYADDR[4:0] Strap BIST Sequence select PSR15 selected PSR9 selected. BIST Test Status BIST pass BIST fail. Latched, cleared by write to BIST_ START bit. ...
Page 42
... Force 10Mb Polarity Correction Force inverted polarity Normal polarity. RO/LH 10Mb Polarity Status: This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSIS register Inverted Polarity detected Correct Polarity detected. ...
Page 43
Table 23. CD Test Register (CDCTRL), Address 0x1B Bit Bit Name Default 15 CD_ENABLE DCDCOMP FIL_TTL RESERVED none RISETIME Strap RESERVED none FALLTIME Strap, RW ...
Page 44
Electrical Specifications Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature (T ) STG Lead Temp. (TL) (Soldering, 10 sec) ESD Rating (R = 1.5k, C ...
Page 45
Symbol Pin Types Parameter V TD 100M Transmit TPTDsym Voltage Symmetry V TD 10M Transmit TPTD_10 Voltage C I CMOS Input IN1 Capacitance SD RD 100BASE-TX THon Signal detect turn- on threshold SD RD 100BASE-TX THoff Signal detect turn- off ...
Page 46
Reset Timing Clock HARDWARE RSTN MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T1.0.1 Post RESET Stabilization time prior to MDC preamble for regis- ter accesses T1.0.2 Hardware Configuration ...
Page 47
PGM Clock Timing X1 TX_CLK Parameter Description T2.0.1 TX_CLK Duty Cycle 6.3 MII Serial Management Timing MDC MDIO (output) MDC MDIO (input) Parameter Description T3.0.1 MDC to MDIO (Output) Delay Time T3.0.2 MDIO (Input) to MDC Setup Time T3.0.3 ...
Page 48
Mb/s Timing 6.4.1 100 Mb/s MII Transmit Timing TX_CLK TXD[3:0] TX_EN TX_ER Parameter Description T4.1.1 TXD[3:0], TX_EN, TX_ER Data Setup to TX_CLK T4.1.2 TXD[3:0], TX_EN, TX_ER Data Hold from TX_CLK 6.4.2 100 Mb/s MII Receive Timing T4.2.1 RX_CLK ...
Page 49
Transmit Packet Latency Timing TX_CLK TX_EN TXD TD Parameter Description T4.3.1 TX_CLK to TD Latency Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the ...
Page 50
Transmit Timing (t +1 rise TD T4.5.2 TD eye pattern Parameter Description T4.5.1 100 Mb and t R 100 Mb/s t and t Mismatch R F T4.5.2 100 Mb/s TD Transmit Jitter Note1: Normal Mismatch is ...
Page 51
Receive Packet Latency Timing RD IDLE T4.6.1 CRS RXD[3:0] RX_DV RX_ER/RXD[4] Parameter Description T4.6.1 Carrier Sense ON Delay T4.6.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first bit of ...
Page 52
Mb/s Timing 6.5.1 10 Mb/s MII Transmit Timing TX_CLK TXD[3:0] TX_EN Parameter Description T5.1.1 TXD[3:0], TX_EN Data Setup to TX_CLK T5.1.2 TXD[3:0], TX_EN Data Hold from TX_CLK 6.5.2 10 Mb/s MII Receive Timing T5.2.1 RX_CLK RXD[3:0] RX_DV Parameter ...
Page 53
Transmit Timing (Start of Packet) TX_CLK TX_EN TXD[0] TPTD Parameter Description T5.3.1 Transmit Enable Setup Time from the Falling Edge of TX_CLK T5.3.2 Transmit Data Setup Time from the Falling Edge of TX_CLK T5.3.3 Transmit Data Hold Time ...
Page 54
Receive Timing (Start of Packet) TPRD CRS RX_CLK RXD[0] RX_DV Parameter Description T5.5.1 Carrier Sense Turn On Delay (TPRD to CRS) T5.5.2 Decoder Acquisition Time T5.5.3 Receive Data Latency T5.5.4 SFD Propagation Delay Note: 10BASE-T receive Data Latency ...
Page 55
Mb/s Heartbeat Timing TXE TXC COL Parameter Description T5.7.1 CD Heartbeat Delay T5.7.2 CD Heartbeat Duration 6.5.8 10 Mb/s Jabber Timing TXE TPTD COL Parameter Description T5.8.1 Jabber Activation Time T5.8.2 Jabber Deactivation Time 6.5.9 10BASE-T Normal Link ...
Page 56
Auto-Negotiation Fast Link Pulse (FLP) Timing T5.10.1 Fast Link Pulse(s) T5.10.4 Parameter Description T5.10.1 Clock, Data Pulse Width T5.10.2 Clock Pulse to Clock Pulse Period T5.10.3 Clock Pulse to Data Pulse Period T5.10.4 Number of Pulses in a Burst ...
Page 57
Loopback Timing 6.6.1 100 Mb/s Internal Loopback Mode TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] Parameter Description T6.1.1 TX_EN to RX_DV Loopback Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial ...
Page 58
Mb/s Internal Loopback Mode TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] Parameter Description T6.2.1 TX_EN to RX_DV Loopback Note: Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN. T6.2.1 Notes 58 Min Typ ...
Page 59
... Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) H/W or S/W Reset (with PHYAD = 00000) MODE Parameter Description T7.0.1 From software clear of bit 10 in the BMCR register to the transi- tion from Isolate to Normal Mode T7.0.2 From Deassertion of S/W or H/W ...
Page 60
... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...