DP83846AVHG63SN National Semiconductor, DP83846AVHG63SN Datasheet - Page 14

• Manufacturer Part Number: DP83846AVHG63SN
• Manufacturer: National Semiconductor

Specifications of DP83846AVHG63SN

• Lead Free Status / RoHS Status: Not Compliant

200 Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to full-
duplex operation, the DP83846A disables its own internal
collision sensing and reporting functions and modifies the
behavior of Carrier Sense (CRS) such that it indicates only
receive activity. This allows a full-duplex capable MAC to
operate properly.
All modes of operation (100BASE-TX and 10BASE-T) can
run either half-duplex or full-duplex. Additionally, other than
CRS and Collision reporting, all remaining MII signaling
remains the same regardless of the selected duplex mode.
It is important to understand that while Auto-Negotiation
with the use of Fast Link Pulse code words can interpret
and configure to full-duplex operation, parallel detection
can not recognize the difference between full and half-
duplex from a fixed 10 Mb/s or 100 Mb/s link partner over
twisted pair. As specified in 802.3u, if a far-end link partner
is transmitting forced full duplex 100BASE-TX for example,
the parallel detection state machine in the receiving station
would be unable to detect the full duplex capability of the
far-end link partner and would negotiate to a half duplex
100BASE-TX configuration (same scenario for 10 Mb/s).
2.5 MII Isolate Mode
The DP83846A can be put into MII Isolate mode by writing
to bit 10 of the BMCR register. In addition, the MII isolate
mode can be selected by strapping in Physical Address 0.
It should be noted that selecting Physical Address 0 via an
MDIO write to PHYCTRL will not put the device in the MII
isolate mode.
When in the MII isolate mode, the DP83846A does not
respond to packet data present at TXD[3:0], TX_EN, and
TX_ER inputs and presents a high impedance on the
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and
CRS outputs. The DP83846A will continue to respond to all
management transactions.
While in Isolate mode, the TD outputs will not transmit
packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
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2.6 Loopback
The DP83846A includes a Loopback Test mode for facili-
tating system diagnostics. The Loopback mode is selected
through bit 14 (Loopback) of the Basic Mode Control Reg-
ister (BMCR). Writing 1 to this bit enables MII transmit data
to be routed to the MII receive outputs. Loopback status
may be checked in bit 3 of the PHY Status Register
(PHYSTS). While in Loopback mode the data will not be
transmitted onto the media in 100 Mb/s mode. To ensure
that the desired operating mode is maintained, Auto-Nego-
tiation should be disabled before selecting the Loopback
mode.
During 10BASE-T operation, in order to be standard com-
pliant, the loopback mode loops MII transmit data to the MII
receive data, however, Link Pulses are not looped back. In
100BASE-TX Loopback mode the data is routed through
the PCS and PMA layers into the PMD sublayer before it is
looped back. In addition to serving as a board diagnostic,
this mode serves as a functional verification of the device.
2.7 BIST
The DsPHYTER incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diagnos-
tics. The BIST circuit can be utilized to test the integrity of
the transmit and receive data paths. BIST testing can be
performed with the part in the internal loopback mode or
externally looped back using a loopback cable fixture.
The BIST is implemented with independent transmit and
receive paths, with the transmit block generating a continu-
ous stream of a pseudo random sequence. The user can
select a 9 bit or 15 bit pseudo random sequence from the
PSR_15 bit in the PHY Control Register (PHYCTRL). The
looped back data is compared to the data generated by the
BIST Linear Feedback Shift Register (LFSR, which gener-
ates a pseudo random sequence) to determine the BIST
pass/fail status.
The pass/fail status of the BIST is stored in the BIST status
bit in the PHYCTRL register. The status bit defaults to 0
(BIST fail) and will transition on a successful comparison. If
an error (mis-compare) occurs, the status bit is latched and
is cleared upon a subsequent write to the Start/Stop bit.
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