DP83846AVHG63SN National Semiconductor, DP83846AVHG63SN Datasheet - Page 8

• Manufacturer Part Number: DP83846AVHG63SN
• Manufacturer: National Semiconductor

Specifications of DP83846AVHG63SN

• Lead Free Status / RoHS Status: Not Compliant

AN_EN
AN_1
AN_0
RX_ER/PAUSE_EN
CRS/LED_CFG
Signal Name
S, O, PU
S, O, PU
Type
S, O
PU
,
LQFP Pin #
27
26
25
46
61
Auto-Negotiation Enable: When high enables Auto-Negotiation
with the capability set by ANO and AN1 pins. When low, puts the
part into Forced Mode with the capability set by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or advertised oper-
ating mode of the DP83846A according to the following table. The
value on these pins is set by connecting the input pins to GND (0)
or V
connected directly to GND or V
The value set at this input is latched into the DP83846A at Hard-
ware-Reset.
The float/pull-down status of these pins are latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset. After reset is deasserted, these
pins may switch to outputs so if pull-ups or pull-downs are imple-
mented, they should be pulled through a 5k resistor.
The default is 111 since these pins have pull-ups.
PAUSE ENABLE: This strapping option allows advertisement of
whether or not the DTE(MAC) has implemented both the optional
MAC control sublayer and the pause function as specified in clause
31 and annex 31B of the IEEE 802.3x specification (Full Duplex
Flow Control).
When left floating the Auto-Negotiation Advertisement Register will
be set to 0, indicating that Full Duplex Flow Control is not supported.
When tied low through a 5 k
Register will be set to 1, indicating that Full Duplex Flow Control is
supported.
The float/pull-down status of this pin is latched into the Auto-Nego-
tiation Advertisement Register during Hardware-Reset.
LED CONFIGURATION: This strapping option defines the polarity
and function of the FDPLX LED pin.
See Section 2.3 for further descriptions of this strapping option.
CC
8
(1) through 5 k
AN_EN AN1
AN_EN AN1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
resistors. These pins should NEVER be
Description
AN0
AN0
0
1
0
1
0
1
0
1
the Auto-Negotiation Advertisement
CC.
10BASE-T, Half-Duplex
10BASE-T, Full-Duplex
100BASE-TX, Half-Duplex
100BASE-TX, Full-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Advertised Mode
Forced Mode
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