DP83846AVHG63SN National Semiconductor, DP83846AVHG63SN Datasheet - Page 5

• Manufacturer Part Number: DP83846AVHG63SN
• Manufacturer: National Semiconductor

Specifications of DP83846AVHG63SN

• Lead Free Status / RoHS Status: Not Compliant

1.0 Pin Descriptions
The DP83846A pins are classified into the following inter-
face categories (each interface is described in the sections
that follow):
— MII Interface
— 10/100 Mb/s PMD Interface
— Clock Interface
— Special Connect Pins
— LED Interface
— Strapping Options/Dual Function pins
— Reset
— Power and Ground pins
Note: Strapping pin option (BOLD) Please see Section 1.6
for strap definitions.
1.1 MII Interface
MDC
MDIO
CRS/LED_CFG
COL
TX_CLK
TXD[3]
TXD[2]
TXD[1]
TXD[0]]
TX_EN
TX_ER
RX_CLK
Signal Name
I/O, OD
O, PU
Type
O, S
O
O
I
I
I
I
59, 58, 55, 54 TRANSMIT DATA: Transmit data MII input pins that accept nibble
LQFP Pin #
37
36
61
60
51
52
50
45
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be asyn-
chronous to transmit and receive clocks. The maximum clock rate is
25 MHz with no minimum clock rate.
MANAGEMENT DATA I/O: Bi-directional management instruc-
tion/data signal that may be sourced by the station management en-
tity or the PHY. This pin requires a 1.5 k
CARRIER SENSE: Asserted high to indicate the presence of carrier
due to receive or transmit activity in 10BASE-T or 100BASE-TX Half
Duplex Modes, while in full duplex mode carrier sense is asserted to
indicate the presence of carrier due only to receive activity.
COLLISION DETECT: Asserted high to indicate detection of a colli-
sion condition (simultaneous transmit and receive activity) in 10
Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with Heartbeat enabled this
pin are also asserted for a duration of approximately 1 s at the end
of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal
is always logic 0. There is no heartbeat function during 10 Mb/s full
duplex operation.
TRANSMIT CLOCK: 25 MHz Transmit clock outputs in 100BASE-
TX mode or 2.5 MHz in 10BASE-T mode derived from the 25 MHz
reference clock.
data synchronous to the TX_CLK (2.5 MHz in 10BASE-T Mode or
25 MHz in 100BASE-TX mode.
TRANSMIT ENABLE: Active high input indicates the presence of
valid nibble data on data inputs, TXD[3:0] for both 100 Mb/s or 10
Mb/s nibble mode.
TRANSMIT ERROR: In 100MB/s mode, when this signal is high and
the corresponding TX_EN is active the HALT symbol is substituted
for data.
In 10 Mb/s this input is ignored.
RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks
for 100BASE-TX mode and 2.5 MHz for 10BASE-T nibble mode.
5
Note: All DP83846A signal pins are I/O cells regardless of
the particular use. Below definitions define the functionality
of the I/O cells for each pin.
Type: I
Type: O
Type: I/O
Type OD
Type: PD,PU Internal Pulldown/Pullup
Type: S
Inputs
Outputs
Input/Output
Open Drain
Strapping Pin (All strap pins except PHY-
AD[0:4] have internal pull-ups or pull-
downs. If the default strap value is needed
to be changed then an external 5 k resistor
should be used. Please see Table 1.6 on
page 7 for details.)
Description
pullup resistor.
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