DP83846AVHG63SN National Semiconductor, DP83846AVHG63SN Datasheet - Page 24

• Manufacturer Part Number: DP83846AVHG63SN
• Manufacturer: National Semiconductor

Specifications of DP83846AVHG63SN

• Lead Free Status / RoHS Status: Not Compliant

A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame
(MDF) or patch panel in the wiring closet.
The inverse polarity condition is latched in the 10BTSCR
register. The DP83846A's 10BASE-T transceiver module
corrects for this error internally and will continue to decode
received data correctly. This eliminates the need to correct
the wiring error immediately.
The user is cautioned that if Auto Polarity Detection and
Correction is disabled and inverted Polarity is detected but
not corrected, the DsPHYTER may falsely report Good
Link status and allow Transmission and Reception of
inverted data. It is recommended that Auto Polarity Detec-
tion and Correction not be disabled during normal opera-
tion.
3.4.7 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83846A, as the required signal conditioning is inte-
grated into the device.
Only isolation/step-up transformers and impedance match-
ing resistors are required for the 10BASE-T transmit and
receive interface. The internal transmit filtering ensures
that all the harmonics in the transmit signal are attenuated
by at least 30 dB.
3.4.8 Transmitter
The encoder begins operation when the Transmit Enable
input (TX_EN) goes high and converts NRZ data to pre-
emphasized Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is
encoded for the transmit-driver pair (TD ). TXD must be
TD+
TD-
RD+
RD-
54.9
Figure 9. 10/100 Mb/s Twisted Pair Interface
54.9
0.1 F
49.9
24
valid on the rising edge of Transmit Clock (TX_CLK).
Transmission ends when TX_EN deasserts. The last tran-
sition is always positive; it occurs at the center of the bit cell
if the last bit is a one, or at the end of the bit cell if the last
bit is a zero.
3.4.9 Receiver
The decoder consists of a differential receiver and a PLL to
separate a Manchester encoded data stream into internal
clock signals and data. The differential input must be exter-
nally terminated with a differential 100
work to accommodate UTP cable. The impedance of RD±
(typically 1.1K ) is in parallel with the two 54.9
as is shown in Figure 9 below to approximate the 100
termination.
The decoder detects the end of a frame when no additional
mid-bit transitions are detected. Within one and a half bit
times after the last bit, carrier sense is de-asserted.
3.5 TPI Network Circuit
Figure 9 shows the recommended circuit for a 10/100 Mb/s
twisted pair interface. Below is a partial list of recom-
mended transformers. Is is important that the user realize
that variations with PCB and component characteristics
requires that the application be tested to ensure that the
circuit meets the requirements of the intended application.
Pulse H1012B, PE-68515L
Halo TG22-S052ND
Valor PT4171
BELFUSE S558-5999-K2
BELFUSE S558-5999-46
49.9
0.1µF*
0.1µF*
Vdd
the transformer center taps
* Place capacitors close to
Common Mode Chokes may
1:1
1:1
be required.
T1
termination net-
www.national.com
RD-
RD+
TD-
TD+
RJ45
resistors