DP83846AVHG63SN National Semiconductor, DP83846AVHG63SN Datasheet - Page 43

• Manufacturer Part Number: DP83846AVHG63SN
• Manufacturer: National Semiconductor

Specifications of DP83846AVHG63SN

• Lead Free Status / RoHS Status: Not Compliant

Bit
7:5
1:0
15
14
13
12
11
10
9
8
4
3
2
10MEG_PATT_GAP
CDPATTSEL[1:0]
CDPATTEN_100
RESERVED[2:0]
CDPATTEN_10
CD_ENABLE
RESERVED
RESERVED
CDTESTEN
DCDCOMP
FALLTIME
RISETIME
Bit Name
FIL_TTL
Table 23. CD Test Register (CDCTRL), Address 0x1B
Strap, RW
Strap, RW
none, RW
none, RW
000, RW
Default
00, RW
1, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
CD Enable:
1 = CD Enabled - power-down mode, outputs high impedance.
0 = CD Disabled.
Duty Cycle Distortion Compensation:
1 = Increases the amount of DCD compensation.
Waveshaper Current Source Test:
To check ability of waveshaper current sources to switch on/off.
1 = Test mode; waveshaping is done, but the output is a square
wave. All sources are either on or off.
0 = Normal mode; sinusoidal.
Reserved: This bit should be written with a 0 if write access is re-
quired on this register.
CD Rise Time Control:
Reserved: This bit should be written with a 0 if write access is re-
quired on this register.
CD Fall Time Control:
CD Test Mode Enable:
1 = Enable CD test mode - differs based on speed of operation
(10/100Mb).
0 = Normal operation.
RESERVED:
Must be zero.
CD Pattern Enable for 10meg:
1 = Enabled.
0 = Disabled.
CD Pattern Enable for 100meg:
1 = Enabled.
0 = Disabled.
Defines gap between data or NLP test sequences:
1 = 15 s.
0 = 10 s.
CD Pattern Select[1:0]:
If CDPATTEN_100 = 1:
00 = All 0’s (True quiet)
01 = All 1’s
10 = 2 1’s, 2 0’s repeating pattern
11 = 14 1’s, 6 0’s repeating pattern
If CDPATTEN_10 = 1:
00 = Data, EOP0 sequence
01 = Data, EOP1 sequence
10 = NLPs
11 = Constant Manchester 1s (10mhz sine wave) for harmonic dis-
tortion testing.
43
Description
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