DP83846AVHG63SN National Semiconductor, DP83846AVHG63SN Datasheet - Page 12

• Manufacturer Part Number: DP83846AVHG63SN
• Manufacturer: National Semiconductor

Specifications of DP83846AVHG63SN

• Lead Free Status / RoHS Status: Not Compliant

The BMSR also provides status on:
— Whether Auto-Negotiation is complete
— Whether the Link Partner is advertising that a remote
— Whether valid link has been established
— Support for Management Frame Preamble suppression
The Auto-Negotiation Advertisement Register (ANAR) indi-
cates the Auto-Negotiation abilities to be advertised by the
DP83846A. All available abilities are transmitted by default,
but any ability can be suppressed by writing to the ANAR.
Updating the ANAR to suppress an ability is one way for a
management agent to change (force) the technology that is
used.
The
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER) indi-
cates additional Auto-Negotiation status. The ANER pro-
vides status on:
— Whether a Parallel Detect Fault has occurred
— Whether the Link Partner supports the Next Page func-
— Whether the DP83846A supports the Next Page function
— Whether the current page being exchanged by Auto-Ne-
— Whether the Link Partner supports Auto-Negotiation
2.1.3 Auto-Negotiation Parallel Detection
The DP83846A supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to moni-
tor the receive signal and report link status to the Auto-
Negotiation function. Auto-Negotiation uses this informa-
tion to configure the correct technology in the event that the
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASE-
T PMAs recognize as valid link signals.
If the DP83846A completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may deter-
mine that negotiation completed via Parallel Detection by
reading a zero in the Link Partner Auto-Negotiation Able bit
once the Auto-Negotiation Complete bit is set. If configured
for parallel detect mode and any condition other than a sin-
gle good link occurs then the parallel detect fault bit will set.
2.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted
at any time by setting bit 9 (Restart Auto-Negotiation) of the
BMCR to one. If the mode configured by a successful Auto-
Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configu-
ration for the link. This function ensures that a valid config-
uration is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a manage-
ment agent, will cause the DP83846A to halt any transmit
fault has occurred
tion
gotiation has been received
Auto-Negotiation
Link
Partner
Ability
Register
12
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83846A
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.
2.1.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83846A has been initial-
ized upon power-up as a non-auto-negotiating device
(forced technology), and it is then required that Auto-Nego-
tiation or re-Auto-Negotiation be initiated via software,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register must first be cleared and then set for any Auto-
Negotiation function to take effect.
2.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to com-
plete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to Auto-Negotia-
tion.
2.2 PHY Address and LEDs
The 5 PHY address inputs pins are shared with the LED
pins as shown below.
The DP83846A can be set to respond to any of 32 possible
PHY addresses. Each DP83846A or port sharing an MDIO
bus in a system must have a unique physical address.
Refer to Section 3.1.4, PHY Address Sensing section for
more details.
The state of each of the PHYAD inputs latched into the
PHYCTRL register bits [4:0] at system power-up/reset
depends on whether a pull-up or pull-down resistor has
been installed for each pin. For further detail relating to the
latch-in timing requirements of the PHY Address pins, as
well as the other hardware configuration pins, refer to the
Reset summary in Section 4.0.
Since the PHYAD strap options share the LED output pins,
the external components required for strapping and LED
usage must be considered in order to avoid contention.
Specifically, when the LED outputs are used to drive LEDs
directly, the active state of each output driver is dependent
on the logic level sampled by the corresponding PHYAD
input upon power-up/reset. For example, if a given PHYAD
input is resistively pulled low then the corresponding output
will be configured as an active high driver. Conversely, if a
given PHYAD input is resistively pulled high, then the cor-
responding output will be configured as an active low
Pin #
33
32
31
30
29
28
Table 2. PHY Address Mapping
will
PHYAD Function
PHYAD0
PHYAD1
PHYAD2
PHYAD3
PHYAD4
resume
n/a
Auto-Negotiation
LED Function
RX Activity
TX Activity
Good Link
www.national.com
Duplex
Speed
COL
after
the