FW82801BA S L4HM Intel, FW82801BA S L4HM Datasheet - Page 261

• Manufacturer Part Number: FW82801BA S L4HM
• Manufacturer: Intel

Specifications of FW82801BA S L4HM

• Lead Free Status / RoHS Status: Not Compliant

5.22.2.20
5.22.2.21
5.22.2.22
5.22.2.23
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Input Slot 6: Optional Dedicated Microphone
Input Slots 7–11: Reserved
Input Slot 12: I/O Status
Record Data
Input slot 6 is a third PCM system input channel available for dedicated use by a microphone. This
input channel supplements a true stereo output which enables more precise echo cancellation
algorithm for speakerphone applications. The ICH5 supports 16-bit resolution for slot 6 input.
Input frame slots 7
the AC ’97 Specification, Version 2.3.
The status of the GPIOs configured as inputs are to be returned on this slot in every frame. The data
returned on the latest frame is accessible to software by reading the register at offset 54h/D4h in the
codec I/O space. Only the 16 MSBs are used to return GPI status. In order for GPI events to cause
an interrupt, both the 'sticky' and 'interrupt' bits must be set for that particular GPIO pin in regs 50h
and 52h. Therefore, the interrupt will be signalled until it has been cleared by the controller, which
can be much longer than one frame.
Reads from 54h/D4h are not transmitted across the link in slot 1 and 2. The data from the most
recent slot 12 is returned on reads from offset 54h/D4h.
Register Access
In the ICH5 implementation of the AC-link, up to three codecs can be connected to the SDOUT
pin. The following mechanism is used to address the primary, secondary, and tertiary codecs
individually.
The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of
slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for
slots 1 and 2 must be set in slot 0, as shown in
address, and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should
be valid since only an address is transmitted. For I/O reads only slot 1 valid bit is set, while for I/O
writes both slots 1 and 2 valid bits are set.
The secondary and tertiary codec registers are accessed using slots 1 and 2 as described above,
however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bits [1:0]
(bit 0 and bit 1 of slot 0) is set to a non-zero value. This allows the secondary or tertiary codec to
monitor the slot valid bits of slots 1and 2, and bits [1:0] of slot 0 to determine if the access is
directed to the secondary or tertiary codec. If the register access is targeted to the secondary or
tertiary codec, slot 1 and 2 will contain the address and data for the register access. Since slots 1
and 2 are marked invalid, the primary codec will ignore these accesses.
–
11 are reserved for future use and should be stuffed with 0s by the codec, per
Table
128. Slot 1 is used to transmit the register
Functional Description
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