FW82801BA S L4HM Intel, FW82801BA S L4HM Datasheet - Page 463

• Manufacturer Part Number: FW82801BA S L4HM
• Manufacturer: Intel

Specifications of FW82801BA S L4HM

• Lead Free Status / RoHS Status: Not Compliant

12.1.4
12.1.5
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS—PCI Status Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
effect.
RID—Revision Identification Register
(USB—D29:F0/F1/F2/F3)
Address Offset:
Default Value:
15:14
10:9
Bit
2:0
Bit
7:0
13
12
11
8
7
6
5
4
3
Reserved as 00b. Read Only.
Received Master Abort (RMA) — R/WC.
0 = No master abort generated by USB.
1 = USB, as a master, generated a master abort.
Reserved. Always read as 0.
Signaled Target Abort (STA) — R/WC.
0 = Intel
1 = USB function is targeted with a transaction that the ICH5 terminates with a target abort.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for DEVSEL#
assertion. These read only bits indicate the ICH5's DEVSEL# timing when performing a positive
decode. ICH5 generates DEVSEL# with medium timing for USB.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable — RO. Hardwired to 0.
Capabilities List — RO. Hardwired to 0.
Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the input of the
enable/disable logic.
0 = Interrupt is deasserted.
1 = Interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
Reserved
Revision ID — RO.These bits contain device stepping information and are hardwired to the default
value.
NOTE: Refer to the latest Intel
Identification register.
®
ICH5 did Not terminate transaction for USB function with a target abort.
06
0280h
08h
See bit description
–
07h
®
ICH5 / ICH5R Specification Update for the value of the Revision
Description
Description
Attribute:
Size:
Attribute:
Size:
UHCI Controllers Registers
R/WC, RO
16 bits
RO
8 bits
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