FW82801BA S L4HM Intel, FW82801BA S L4HM Datasheet - Page 306

• Manufacturer Part Number: FW82801BA S L4HM
• Manufacturer: Intel

Specifications of FW82801BA S L4HM

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.9
8.1.10
8.1.11
8.1.12
306
HEADTYP—Header Type Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
PBUS_NUM—Primary Bus Number Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
SBUS_NUM—Secondary Bus Number Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
SUB_BUS_NUM—Subordinate Bus Number Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
Bit
6:0
Bit
7:0
Bit
7:0
Bit
7:0
7
Multi-Function Device (MFD) — RO. This bit is 0 to indicate a single function device.
Header Type (HTYPE) — RO. This 8-bit field identifies the header layout of the configuration space,
which is a PCI-to-PCI bridge in this case.
Primary Bus Number — RO. This field indicates the bus number of the hub interface and is
hardwired to 00h.
Secondary Bus Number — R/W. This field indicates the bus number of PCI.
NOTE: When this number is equal to the primary bus number (i.e., bus #0), the Intel
Subordinate Bus Number — R/W. This field specifies the highest PCI bus number below the hub
interface to PCI bridge. If a Type 1 configuration cycle from the hub interface does not fall in the
Secondary-to-Subordinate Bus ranges of Device 30, the Intel
to the hub interface.
hub interface configuration cycles to this bus number as Type 1 configuration cycles on PCI.
0Eh
01h
18h
00h
19h
00h
1A
00h
Description
Description
Description
Description
Intel
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5 indicates a master abort back
RO
8 bits
RO
8 bits
R/W
8 bits
R/W
8 bits
®
ICH5 will run