FW82801BA S L4HM Intel, FW82801BA S L4HM Datasheet - Page 436

• Manufacturer Part Number: FW82801BA S L4HM
• Manufacturer: Intel

Specifications of FW82801BA S L4HM

• Lead Free Status / RoHS Status: Not Compliant

SATA Controller Registers (D31:F2)
11.1.4
436
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS — PCI Status Register
(SATA–D31:F2)
Address Offset:
Default Value:
effect.
10:9
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated.
1 = Bus Master IDE interface function, as a master, generated a master abort.
Reserved as 0 — RO.
Signaled Target Abort (STA) — RO. Reserved as 0.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
Data Parity Error Detected (DPED) — RO. For Intel
completions received from SiBUS where there is a parity error.
1 = SATA controller, as a master, either detects a parity error or sees the parity error line asserted,
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66 MHz Capable (66MHZ_CAP) — RO. Reserved as 1.
Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities list. The
minimum requirement for the capabilities list must be PCI power management for the SATA
controller.
0 = A capabilities list is not present
1 = A capabilities list is present
NOTE: This bit is hardwired to 0.
Interrupt Status (INTS)— RO. This bit is independent of the state of the Interrupt Disable bit in the
command register.
0 = Interrupt is cleared.
1 = Interrupt/MSI is asserted.
Reserved
and the parity error response bit (bit 6 of the command register) is set.
06
02A0h
–
07h
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5, this bit can only be set on read
R/WC, RO
16 bits