FW82801BA S L4HM Intel, FW82801BA S L4HM Datasheet - Page 440

• Manufacturer Part Number: FW82801BA S L4HM
• Manufacturer: Intel

Specifications of FW82801BA S L4HM

• Lead Free Status / RoHS Status: Not Compliant

SATA Controller Registers (D31:F2)
11.1.14
11.1.15
11.1.16
440
BAR — Legacy Bus Master Base Address Register
(SATA–D31:F2)
Address Offset:
Default Value:
The Bus Master IDE interface function uses Base Address register 5 to request a 16-byte IO space
to provide a software interface to the Bus Master functions. Only 12 bytes are actually used
(6 bytes for primary, 6 bytes for secondary). Only bits [15:4] are used to decode the address.
SVID—Subsystem Vendor Identification Register
(SATA–D31:F2)
Address Offset:
Default Value:
Lockable:
SID—Subsystem Identification Register
(SATA–D31:F2)
Address Offset:
Default Value:
Lockable:
31:16
15:0
15:0
15:4
Bit
Bit
Bit
3:1
0
Subsystem Vendor ID (SVID) — R/WO. The SVID register, in combination with the Subsystem ID
(SID) register, enables the operating system (OS) to distinguish subsystems from each other.
Software (BIOS) sets the value in this register. After that, the value can be read, but subsequent
writes to this register have no effect.
Subsystem ID (SID) —
operating system (OS) to distinguish subsystems from each other. Software (BIOS) sets the value in
this register. After that, the value can be read, but subsequent writes to this register have no effect.
Reserved
Base Address — R/W. This field provides the base address of the I/O space (16 consecutive I/O
locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O space.
20h
00000001h
2Ch
0000h
No
2Eh
0000h
No
–
–
–
23h
2Fh
2Dh
R/WO
. The SID register, in combination with the SVID register, enables the
Description
Description
Intel
Description
Attribute:
Size:
Attribute:
Size:
Power Well: Core
Attribute:
Size:
Power Well: Core
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, RO
32 bits
R/WO
16 bits
R/WO
16 bits