FW82801BA S L4HM Intel, FW82801BA S L4HM Datasheet - Page 343

• Manufacturer Part Number: FW82801BA S L4HM
• Manufacturer: Intel

Specifications of FW82801BA S L4HM

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
NOTE:
1. Software must always disable all functionality within the function before disabling the configuration space.
2. Configuration writes to internal devices, when the devices are disabled, are illegal and may cause undefined
results.
Bit
5
4
3
2
1
0
D31_F5_Disable — R/W. Software sets this bit to disable the AC ’97 audio controller function. BIOS
must not enable I/O or memory address space decode, interrupt generation, or any other
functionality of functions that are to be disabled
0 = AC ’97 audio controller is enabled
1 = AC ’97 audio controller is disabled
Reserved
D31_F3_Disable — R/W. Software sets this bit to disable the SMBus Host controller function. BIOS
must not enable I/O or memory address space decode, interrupt generation, or any other
functionality of functions that are to be disabled
0 = SMBus controller is enabled
1 = SMBus controller is disabled
D31_F2_Disable — R/W. Software sets this bit to disable the SATA Host controller function. BIOS
must not enable I/O or memory address space decode, interrupt generation, or any other
functionality of functions that are to be disabled
0 = SATA controller is enabled
1 = SATA controller is disabled
D31_F1_Disable — R/W. Software sets this bit to disable the IDE controller function. BIOS must not
enable I/O or memory address space decode, interrupt generation, or any other functionality of
functions that are to be disabled
0 = IDE controller is enabled
1 = IDE controller is disabled
SMB_FOR_BIOS — R/W. This bit is used in conjunction with bit 3 in this register.
0 = No effect.
1 = Allows the SMBus I/O space to be accessible by software when bit 3 in this register is set. The
PCI configuration space is hidden in this case. Note that if bit 3 is set alone, the decode of both
SMBus PCI configuration and I/O space will be disabled.
.
Description
LPC Interface Bridge Registers (D31:F0)
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.
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