FW82801BA S L4HM Intel, FW82801BA S L4HM Datasheet - Page 53

• Manufacturer Part Number: FW82801BA S L4HM
• Manufacturer: Intel

Specifications of FW82801BA S L4HM

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 7. PCI Interface Signals (Sheet 2 of 3)
82801EB ICH5 / 82801ER ICH5R Datasheet
REQ[0:3]#
GNT[0:3]#
GPIO17#
REQB# /
GNTB# /
REQ4# /
REQ5# /
GNT4# /
GNT5# /
PCICLK
GPIO40
GPIO48
PERR#
TRDY#
STOP#
GPIO1
IRDY#
Name
PAR
Type
I/O
I/O
I/O
I/O
I/O
O
I
I
Initiator Ready: IRDY# indicates the ICH5's ability, as an Initiator, to complete the
current data phase of the transaction. It is used in conjunction with TRDY#. A data
phase is completed on any clock both IRDY# and TRDY# are sampled asserted.
During a write, IRDY# indicates the ICH5 has valid data present on AD[31:0].
During a read, it indicates the ICH5 is prepared to latch data. IRDY# is an input to
the ICH5 when the ICH5 is the Target and an output from the ICH5 when the ICH5
is an Initiator. IRDY# remains tri-stated by the ICH5 until driven by an Initiator.
Target Ready: TRDY# indicates the ICH5's ability as a Target to complete the
current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A
data phase is completed when both TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that the ICH5, as a Target, has placed valid data
on AD[31:0]. During a write, TRDY# indicates the ICH5, as a Target is prepared to
latch data. TRDY# is an input to the ICH5 when the ICH5 is the Initiator and an
output from the ICH5 when the ICH5 is a Target. TRDY# is tri-stated from the
leading edge of PCIRST#. TRDY# remains tri-stated by the ICH5 until driven by a
target.
Stop: STOP# indicates that the ICH5, as a Target, is requesting the Initiator to stop
the current transaction. STOP# causes the ICH5, as an Initiator, to stop the current
transaction. STOP# is an output when the ICH5 is a Target and an input when the
ICH5 is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP#
remains tri-stated until driven by the ICH5.
Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits,
AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH5 counts the number of
1’ within the 36 bits plus PAR and the sum is always even. The ICH5 always
calculates PAR on 36 bits regardless of the valid byte enables. The ICH5 generates
PAR for address and data phases and only guarantees PAR to be valid one PCI
clock after the corresponding address or data phase. The ICH5 drives and tri-
states PAR identically to the AD[31:0] lines except that the ICH5 delays PAR by
exactly one PCI clock. PAR is an output during the address phase (delayed one
clock) for all ICH5 initiated transactions. PAR is an output during the data phase
(delayed one clock) when the ICH5 is the Initiator of a PCI write transaction, and
when it is the Target of a read transaction. ICH5 checks parity when it is the Target
of a PCI write transaction. If a parity error is detected, the ICH5 will set the
appropriate internal status bits, and has the option to generate an NMI# or SMI#.
Parity Error: An external PCI device drives PERR# when it receives data that has
a parity error. The ICH5 drives PERR# when it detects a parity error. The ICH5 can
either generate an NMI# or SMI# upon detecting a parity error (either detected
internally or reported via the PERR# signal when serving as the initiator).
PCI Requests: The ICH5 supports up to six masters on the PCI bus. The REQ4#
pin can instead be used as a GPI. REQ5# is muxed with PC/PCI REQB# (must
choose one or the other, but not both). If not used for PCI or PC/PCI, REQ5#/
REQB# can instead be used as GPIO1.
NOTE: R EQ0# is programmable to have improved arbitration latency for
PCI Grants: The ICH5 supports up to 6 masters on the PCI bus. The GNT4# pin
can instead be used as a GPO. GNT5# is multiplexed with PC/PCI GNTB# (must
choose one or the other, but not both). If not needed for PCI or PC/PCI, GNT5# can
instead be used as a GPIO.
Pull-up resistors are not required on these signals. If pull-ups are used, they should
be tied to the Vcc3_3 power rail. GNTB#/GNT5#/GPIO17 has an internal pull-up.
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on
the PCI Bus.
supporting PCI-based 1394 controllers.
Description
Signal Description
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