FW82801EB Intel, FW82801EB Datasheet - Page 111

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.5.3
5.5.3.1
5.5.4
Intel
®
Table 39. DMA Transfer Size
Table 40. Address Shifting in 16-Bit I/O DMA Transfers
82801EB ICH5 / 82801ER ICH5R Datasheet
Address Shifting When Programmed for 16-Bit
Summary of DMA Transfer Sizes
Table 39
Count Register” indicates that the register contents represents either the number of bytes to transfer
or the number of 16-bit words to transfer. The column labeled “Current Address Increment/
Decrement” indicates the number added to or taken from the Current Address register after each
DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register
will be incremented or decremented.
I/O Count by Words
The ICH5 maintains compatibility with the implementation of the DMA in the PC AT that used the
82C37. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note
that the least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When
programming the Current Address Register (when the DMA channel is in this mode), the Current
Address must be programmed to an even address with the address value shifted right by one bit.
The address shifting is shown in
NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as an
autoinitialize channel. When a channel undergoes autoinitialization, the original values of the
Current Page, Current Address and Current Byte/Word Count Registers are automatically restored
from the Base Page, Address, and Byte/Word Count Registers of that channel following TC. The
Base Registers are loaded simultaneously with the Current Registers by the microprocessor when
the DMA channel is programmed and remain unchanged throughout the DMA service. The mask
bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to
perform another DMA service, without processor intervention, as soon as a valid DREQ is
detected.
8-Bit I/O, Count By Bytes
16-Bit I/O, Count By Words (Address Shifted)
DMA Device Date Size And Word Count
lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word
Address
A[23:17]
Output
A[16:1]
A0
Table
8-Bit I/O Programmed Address
40.
(Ch 0–3)
A[23:17]
A[16:1]
Current Byte/Word Count
A0
Register
Words
Bytes
16-Bit I/O Programmed Address
Functional Description
Increment/Decrement
Current Address
(Ch 5–7)
(Shifted)
A[23:17]
A[15:0]
0
1
1
111